DS_1209F_004
73S1209F Data Sheet
Tables
Table 1: 73S1209F Pinout Description ......................................................................................................... 8
Table 2: MPU Data Memory Map................................................................................................................ 11
Table 3: Flash Special Function Registers ................................................................................................. 13
Table 4: Internal Data Memory Map ........................................................................................................... 14
Table 5: Security Control Registers ............................................................................................................ 17
Table 6: IRAM Special Function Registers Locations................................................................................. 18
Table 7: IRAM Special Function Registers Reset Values........................................................................... 19
Table 8: XRAM Special Function Registers Reset Values ......................................................................... 21
Table 9: PSW Register Flags...................................................................................................................... 22
Table 10: Port Registers .............................................................................................................................23
Table 11: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 25
Table 12: The MCLKCtl Register................................................................................................................ 25
Table 13: The MPUCKCtl Register............................................................................................................. 26
Table 14: The INT5Ctl Register .................................................................................................................. 29
Table 15: The MISCtl0 Register.................................................................................................................. 29
Table 16: The MISCtl1 Register.................................................................................................................. 30
Table 17: The MCLKCtl Register................................................................................................................ 30
Table 18: The PCON Register .................................................................................................................... 31
Table 19: The IEN0 Register....................................................................................................................... 33
Table 20: The IEN1 Register....................................................................................................................... 34
Table 21: The IEN2 Register....................................................................................................................... 34
Table 22: The TCON Register .................................................................................................................... 35
Table 23: The T2CON Register .................................................................................................................. 35
Table 24: The IRCON Register................................................................................................................... 36
Table 25: External MPU Interrupts.............................................................................................................. 36
Table 26: Control Bits for External Interrupts.............................................................................................. 37
Table 27: Priority Level Groups................................................................................................................... 37
Table 28: The IP0 Register ......................................................................................................................... 37
Table 29: The IP1 Register ......................................................................................................................... 38
Table 30: Priority Levels..............................................................................................................................38
Table 31: Interrupt Polling Sequence.......................................................................................................... 38
Table 32: Interrupt Vectors.......................................................................................................................... 38
Table 33: UART Modes............................................................................................................................... 39
Table 34: Baud Rate Generation ................................................................................................................ 39
Table 35: The PCON Register .................................................................................................................... 40
Table 36: The BRCON Register ................................................................................................................. 40
Table 37: The MISCtl0 Register.................................................................................................................. 41
Table 38: The S0CON Register.................................................................................................................. 42
Table 39: The S1CON Register.................................................................................................................. 43
Table 40: The TMOD Register.................................................................................................................... 44
Table 41: TMOD Register Bit Description................................................................................................... 44
Table 42: Timers/Counters Mode Description ............................................................................................ 45
Table 43: The TCON Register .................................................................................................................... 46
Table 44: The IEN0 Register....................................................................................................................... 47
Table 45: The IEN1 Register....................................................................................................................... 47
Table 46: The IP0 Register ......................................................................................................................... 48
Table 47: The WDTREL Register ............................................................................................................... 48
Table 48: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 49
Table 49: UDIR Control Bit.......................................................................................................................... 49
Table 50: Selectable Controls Using the UxIS Bits..................................................................................... 49
Table 51: The USRIntCtl1 Register ............................................................................................................ 50
Table 52: The USRIntCtl2 Register ............................................................................................................ 50
Table 53: The USRIntCtl3 Register ............................................................................................................ 50
Table 54: The USRIntCtl4 Register ............................................................................................................ 50
Table 55: The ACOMP Register ................................................................................................................. 51
Table 56: The INT6Ctl Register .................................................................................................................. 52
Rev. 1.2
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