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72271LA15PFG PDF预览

72271LA15PFG

更新时间: 2024-02-25 22:39:41
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
27页 440K
描述
FIFO, 32KX9, 10ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64

72271LA15PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP, QFP64,.66SQ,32针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.18
最长访问时间:10 ns其他特性:RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH
最大时钟频率 (fCLK):66.7 MHz周期时间:15 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:14 mm内存密度:294912 bit
内存集成电路类型:OTHER FIFO内存宽度:9
湿度敏感等级:3功能数量:1
端子数量:64字数:32768 words
字数代码:32000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX9可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP64,.66SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.02 A子类别:FIFOs
最大压摆率:0.075 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

72271LA15PFG 数据手册

 浏览型号72271LA15PFG的Datasheet PDF文件第21页浏览型号72271LA15PFG的Datasheet PDF文件第22页浏览型号72271LA15PFG的Datasheet PDF文件第23页浏览型号72271LA15PFG的Datasheet PDF文件第24页浏览型号72271LA15PFG的Datasheet PDF文件第25页浏览型号72271LA15PFG的Datasheet PDF文件第26页 
3.3 VOLT CMOS SuperSync FIFO™  
16,384 x 9  
32,768 x9  
IDT72261LA  
IDT72271LA  
ADDENDUM  
DIFFERENCES BETWEEN THE IDT72261LA/72271LA AND IDT72261L/72271L  
IDT has improved the performance of the IDT72261/72271 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part  
is pin-for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences.  
Item  
NEW PART  
OLD PART  
Comments  
IDT72261LA  
IDT72271LA  
IDT72261L  
IDT72271L  
Pin #3  
DC (Don’t Care) - There is  
no restriction on WCLK and  
RCLK. See note 1.  
FS (Frequency Select)  
In the LA part this pin must be tied  
to either VCC or GND and must  
not toggle after reset.  
First Word Latency  
(IDT Standard Mode)  
60ns(2) + tREF + 1 TRCLK(4)  
60ns(2) + tREF + 2 TRCLK(4)  
60ns(2) + tREF + 1 TRCLK(4)  
60ns(2) + tREF + 2 TRCLK(4)  
tFWL1 = 10*Tf(3) + 2TRCLK(4)(ns) First word latency in the LA part  
is a fixed value, independent of  
the frequency of RCLK or WCLK.  
tFWL2 = 10*Tf(3) + 3TRCLK(4)(ns) First word latency in the LA part  
is a fixed value, independent of  
the frequency of RCLK or WCLK.  
tRTF1 = 14*Tf(3) + 3TRCLK(4)(ns) Retransmit latency in the LA part  
is a fixed value, independent of  
the frequency of RCLK or WCLK.  
tRTF2 = 14*Tf(3) + 4TRCLK(4)(ns) Retransmit latency in the LA part  
is a fixed value, independent of  
First Word Latency  
(FWFT Mode)  
Retransmit Latency  
(IDT Standard Mode)  
Retransmit Latency  
(FWFT Mode)  
the frequency of RCLK or WCLK.  
ICC1  
75mA  
20mA  
150mA  
15mA  
Active supply current  
Standby current  
ICC2  
Typical ICC1(5)  
15 + 1.85*fS + 0.02*CL*fS(mA) Not Given  
Typical ICC1 Current calculation  
NOTES:  
1. WCLK and RCLK can vary independently and can be stopped. There is no restriction on operating WCLK and RCLK.  
2. This is tSKEW3.  
3. Tf is the period of the ‘selected clock’.  
4. TRCLK is the cycle period of the read clock.  
5. Typical ICC1 is based on VCC = 5V, tA = 25C, fS = WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching at fS/2, CL = Capacitive Load (in pF).  
IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc.The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
27  
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice  

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