Datasheet > 71V416YS12BEI

71V416YS12BEI

更新时间： 2024-02-11 15:45:48

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
9页	104K
描述
Standard SRAM, 256KX16, 12ns, CMOS, PBGA48

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71V416YS12BEI 数据手册

IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM

4 Meg (256K x 16-Bit)

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)^(1,3)

tWC

ADDRESS

tAW

(2)

tAS

tCW

tBW

BHE, BLE

tWP

tWR

DATAOUT

DATAIN

tDH

tDW

DATAIN VALID

6442 drw 0

Timing Waveform of Write Cycle No. 3

(BHE, BLE Controlled Timing)^(1,3)

tWC

ADDRESS

tAW

(2)

tCW

tAS

tBW

BHE, BLE

tWP

tWR

DATAOUT

DATAIN

tDH

tDW

DATAIN VALID

6442 drw 1

NOTES:

1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.

2. During this period, I/O pins are in the output state, and input signals must not be applied.

3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6.42

1...4 5 678 9

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