5秒后页面跳转
71V416YS10Y8 PDF预览

71V416YS10Y8

更新时间: 2022-12-01 20:14:49
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管
页数 文件大小 规格书
9页 478K
描述
Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44

71V416YS10Y8 数据手册

 浏览型号71V416YS10Y8的Datasheet PDF文件第3页浏览型号71V416YS10Y8的Datasheet PDF文件第4页浏览型号71V416YS10Y8的Datasheet PDF文件第5页浏览型号71V416YS10Y8的Datasheet PDF文件第6页浏览型号71V416YS10Y8的Datasheet PDF文件第8页浏览型号71V416YS10Y8的Datasheet PDF文件第9页 
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM  
4 Meg (256K x 16-Bit)  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,3)  
tWC  
ADDRESS  
CS  
tAW  
(2)  
tAS  
tCW  
tBW  
BHE, BLE  
WE  
tWP  
tWR  
DATAOUT  
DATAIN  
tDH  
t
DW  
DATAIN VALID  
6442 drw 0  
Timing Waveform of Write Cycle No. 3  
(BHE, BLE Controlled Timing)(1,3)  
tWC  
ADDRESS  
CS  
tAW  
(2)  
tCW  
tAS  
tBW  
BHE, BLE  
tWP  
tWR  
WE  
DATAOUT  
tDH  
tDW  
DATAIN  
DATAIN VALID  
6442 drw 1  
NOTES:  
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.  
2. During this period, I/O pins are in the output state, and input signals must not be applied.  
3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.  
6.42  
7

与71V416YS10Y8相关器件

型号 品牌 描述 获取价格 数据表
71V416YS10YG IDT Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-44

获取价格

71V416YS10YGI IDT Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-44

获取价格

71V416YS10YI IDT Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44

获取价格

71V416YS12BE IDT Standard SRAM, 256KX16, 12ns, CMOS, PBGA48, 9 X 9 MM, BGA-48

获取价格

71V416YS12BE8 IDT Standard SRAM, 256KX16, 12ns, CMOS, PBGA48, 9 X 9 MM, BGA-48

获取价格

71V416YS12BEG IDT Standard SRAM, 256KX16, 12ns, CMOS, PBGA48, 9 X 9 MM, ROHS COMPLIANT, BGA-48

获取价格