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71V416YL15BEI PDF预览

71V416YL15BEI

更新时间: 2023-01-03 01:37:20
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
9页 104K
描述
Standard SRAM, 256KX16, 15ns, CMOS, PBGA48, 9 X 9 MM, BGA-48

71V416YL15BEI 数据手册

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IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM  
4 Meg (256K x 16-Bit)  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,3)  
tWC  
ADDRESS  
tAW  
CS  
(2)  
tAS  
tCW  
tBW  
BHE, BLE  
WE  
tWP  
tWR  
DATAOUT  
DATAIN  
tDH  
tDW  
DATAIN VALID  
6442 drw 0  
Timing Waveform of Write Cycle No. 3  
(BHE, BLE Controlled Timing)(1,3)  
tWC  
ADDRESS  
tAW  
CS  
(2)  
tCW  
tAS  
tBW  
BHE, BLE  
tWP  
tWR  
WE  
DATAOUT  
DATAIN  
tDH  
tDW  
DATAIN VALID  
6442 drw 1  
NOTES:  
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.  
2. During this period, I/O pins are in the output state, and input signals must not be applied.  
3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.  
6.42  
7

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