Datasheet > 71V3558

71V3558

更新时间： 2023-12-20 18:44:23

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
29页	332K
描述
3.3V 256K x 18 ZBT Synchronous PipeLined SRAM w/3.3V I/O

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数据手册

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71V3558 数据手册

71V3556, 71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Pin Description Summary

0-A17

Address Inputs

Input

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

Input

Output

Input

I/O

CE1, CE

, CE

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

, BW

CLK

ADV/LD

LBO

TMS

TDI

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

Synchronous

N/A

TCK

Test Clock

TDO

TRST

Test Data Output

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

I/O

-I/O31, I/OP1-I/OP4

Data Input / Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

Static

5281 tbl 01

6.42

Aug.06.21

1 234 5 6 7...29

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