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71M6603-ILR PDF预览

71M6603-ILR

更新时间: 2024-01-27 16:45:10
品牌 Logo 应用领域
美信 - MAXIM 传感器温度传感器监控
页数 文件大小 规格书
19页 374K
描述
On-Chip Temperature Sensor Enables Localized Digital Temperature On-Chip Power Monitoring

71M6603-ILR 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.64
Is Samacsys:N模拟集成电路 - 其他类型:ANALOG CIRCUIT
JESD-30 代码:R-PDSO-G8长度:4.93 mm
湿度敏感等级:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/3.3 V
认证状态:Not Qualified座面最大高度:1.73 mm
子类别:Other Analog ICs最大供电电流 (Isup):1.05 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.5 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.94 mm
Base Number Matches:1

71M6603-ILR 数据手册

 浏览型号71M6603-ILR的Datasheet PDF文件第1页浏览型号71M6603-ILR的Datasheet PDF文件第2页浏览型号71M6603-ILR的Datasheet PDF文件第3页浏览型号71M6603-ILR的Datasheet PDF文件第5页浏览型号71M6603-ILR的Datasheet PDF文件第6页浏览型号71M6603-ILR的Datasheet PDF文件第7页 
PDS_6xxx_010  
71M6xxx Data Sheet  
1
HARDWARE DESCRIPTION  
The 71M6103/71M6113/71M6201/71M6203/71M6601/71M6603 (71M6xxx) remote sensor ICs integrate  
all functional blocks required to implement an isolated front-end with digital communication capability.  
Figure 1 shows the 71M6xxx IC block diagram. The chip includes the following:  
Preamplifier with a fixed gain  
22-bit delta-sigma ADC  
ADC voltage reference  
Temperature sensor  
VCC monitor  
Power-on reset circuitry  
Bidirectional pulse interface  
Active rectifiers for supply-voltage generation from the power pulses provided by the 71M654x  
Digital control section providing control registers for the selection of operation modes  
INP  
ADC  
+
-
VREF  
SHUNT  
INN  
PREAMP  
VBIAS  
-
ADC_CLK  
+
CROSS  
ADC_OUT  
BUFFER  
VCC  
TEMP/VCC  
MONITOR  
BAND  
GAP  
VDD  
1:1.1  
SP  
SN  
IBIAS  
CHOP  
PLL  
PULSEIO  
To  
71M654X  
RD_CLK  
WR_DATA  
RD_DATA  
RD_DATA  
Primary Secondary  
DIGITAL SECTION  
RESET  
POWER  
ON  
RESET  
DATA_IN[15:0]  
OTP MEMORY  
ACTIVE  
RECTI-  
FIERS  
GND VCC  
TEST  
Figure 1: Block Diagram  
2
FUNCTIONAL DESCRIPTION  
During normal operation, the SP and SN pins of the 71M6xxx are connected to the pulse transformer.  
When PLL_FAST = 1 in the 71M654x, power pulses generated by the 71M654x arrive every 610.35ns.  
The PLL in the 71M6xxx locks to these incoming power pulses. The communication between the  
71M654x and the 71M6xxx is synchronized to the multiplexer frames of the 71M654x. The  
communication protocol is Teridian-proprietary, and details are not described in this data sheet. All  
aspects of the communication between the 71M654x and the 71M6xxx are managed on the hardware  
level and they are completely transparent to the user.  
The communication interface can run at two different data rates. Power pulses are generated every  
610.35ns if the PLL_FAST register in the 71M654x is set to 1, and every 1.905µs if PLL_FAST is set to 0.  
The power pulses are 101.7ns wide with PLL_FAST = 1, and 160ns wide with PLL_FAST = 0.  
v1.2  
© 2008–2011 Teridian Semiconductor Corporation  
4
 
 
 

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