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71M6513H-IGTR/F PDF预览

71M6513H-IGTR/F

更新时间: 2024-02-09 16:46:45
品牌 Logo 应用领域
TERIDIAN /
页数 文件大小 规格书
104页 1320K
描述
Analog Circuit,

71M6513H-IGTR/F 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
包装说明:LFQFP,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.36其他特性:ALSO REQUIRES 3.3V DIGITAL SUPPLY
模拟集成电路 - 其他类型:ANALOG CIRCUITJESD-30 代码:S-PQFP-G100
JESD-609代码:e3长度:14 mm
湿度敏感等级:3功能数量:1
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mm

71M6513H-IGTR/F 数据手册

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71M6513/71M6513H  
3-Phase Energy Meter IC  
A Maxim Integrated Products Brand  
DATA SHEET  
AUGUST 2011  
Revision History (Continued)  
Revision  
Date  
Description  
Removed all references to ROM versions. Removed reference to 3rd UART in  
“Hardware Overview” using bit-bang technique. Added note stating that “bit-  
banging” of DIO4/5 is discouraged. Added “A 1,000pF capacitor to GND should  
be connected to this pin” for VBIAS in Analog Pin Descriptions. Added precaution  
regarding I/O RAM locations affected by flash write under “Flash Memory”. Added  
remark in “MPU/CE Communication” on inaccuracy of accumulation interval as  
compared to RTC. Modified CE Interface description. Changed in Electrical Spe-  
cifications: TC1 to +7.0 (VREF section), recommended capacitor values for  
XIN/XOUT and crystal type. Corrected diagram for Rogowski coil (Figure 30).  
Fixed Table 56.  
2.4  
8/17/2007  
Updated package information from IEL (exposed pad LQFP) to IGT/F package  
type (title page, package drawing, and ordering information). Updated Teridian  
street address information. Updated explanation for V3SQSUM register in CE  
Interface Description.  
2.5  
8/12/2008  
Added revision history table to replace separate revision notes.  
Changed information on Wh accuracy on title page. Added section on delay  
compensation in CE Description. Corrected UART description in MPU section.  
Added cautionary note in CE Program and Environment section stating that  
operating CE code with environmental settings other than those specified in the  
data sheet will lead to unpredictable results. Deleted graphs showing typical  
performance over temperature. Added crystal oscillator information in Application  
Information section. Added note in Applications section stating that high source  
impedance sensor circuits should be avoided.  
2.6  
12/10  
Clarified “guaranteed by design” and “tested in production” information in  
Electrical Specifications section.  
Changed font for all SFR and I/O RAM register variables to Times New Roman  
Italic.  
Corrected various typos.  
Added the following:  
- Changed “50ppm/°C” to “40ppm/°C” (page 1).  
- Explanation of scaling factors applied to PPMC and PPMC2 (page 73).  
- Explanation of error bands for temperature compensation (page 82).  
- Precautionary notes regarding the voltage range of the V3 pin (page 88).  
- Precautionary notes for connecting a battery (page 88).  
3
9/11  
Page: 104 of 104  
© 2005-2011 Teridian Semiconductor Corporation  

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