Datasheet > 709189S12PF8

709189S12PF8

更新时间： 2024-01-23 02:02:34

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
15页	177K
描述
TQFP-100, Reel

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技术参数
数据手册

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709189S12PF8 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	TQFP
包装说明：	,	针数：	100
Reach Compliance Code：	not_compliant	风险等级：	5.92
JESD-609代码：	e0	内存集成电路类型：	DUAL-PORT SRAM
湿度敏感等级：	3	峰值回流温度（摄氏度）：	240
端子面层：	Tin/Lead (Sn/Pb)	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

709189S12PF8 数据手册

HIGH-SPEED 64K x 9

IDT709189L

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial: 7.5/9/12ns (max.)

Low-power operation

Full synchronous operation on both ports

– 4ns setup to clock and 0ns hold on all control, data, and

address inputs

◆

– Data input, address, and control registers

– Fast 7.5ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– IDT709189L

Active: 1.2W (typ.)

Standby: 2.5mW (typ.)

– 12ns cycle time, 83MHz operation in Pipelined output mode

TTL- compatible, single 5V (±10%) power supply

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

◆

Flow-Through or Pipelined output mode on either Port via

the FT/PIPE pins

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

◆

Available in a 100-pin Thin Quad Flatpack (TQFP) package

Functional Block Diagram

R/WR

OER

R/WL

OEL

CE0R

CE_1R

CE0L

CE1L

0/1

/PIPEL

0/1

FT/PIPER

I/O0R - I/O8R

I/O0L - I/O8L

I/O

Control

I/O

Control

A15L

A15R

Counter/

Address

Reg.

Counter/

Address

Reg.

MEMORY

ARRAY

A0R

A0L

CLKR

CLKL

ADSR

ADSL

CNTENL

CNTENR

CNTRSTR

CNTRSTL

4848 drw 01

JANUARY 2001

DSC-4848/3

12 3 4 5 6 7...15

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