Datasheet > 7025L15GG

7025L15GG

更新时间： 2024-02-06 06:40:07

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
22页	204K
描述
Dual-Port SRAM

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技术参数
数据手册

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7025L15GG 技术参数

生命周期：	Active	包装说明：	PGA,
Reach Compliance Code：	compliant	风险等级：	5.19
最长访问时间：	15 ns	JESD-30 代码：	S-CPGA-P84
内存密度：	131072 bit	内存集成电路类型：	DUAL-PORT SRAM
内存宽度：	16	功能数量：	1
端子数量：	84	字数：	8192 words
字数代码：	8000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	8KX16	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	PGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	PIN/PEG	端子位置：	PERPENDICULAR
Base Number Matches：	1

7025L15GG 数据手册

HIGH-SPEED

IDT7025S/L

8K x 16 DUAL-PORT

STATIC RAM

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

◆

IDT7025 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = H for BUSY output flag on Master

M/S = L for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Battery backup operation—2V data retention

TTL-compatible, single 5V (±10%) power supply

Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin

Quad Flatpack

Features

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

– Military:20/25/35/55/70ns(max.)

– Industrial: 55ns (max.)

◆

– Commercial:15/17/20/25/35/55ns(max.)

Low-power operation

◆

– IDT7025S

◆

Active:750mW(typ.)

Standby: 5mW (typ.)

– IDT7025L

Active:750mW(typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for multiplexed

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

bus compatibility

FunctionalBlockDiagram

R/W

CEL

CER

I/O8L-I/O15L

I/O0L-I/O7L

I/O8R-I/O15R

I/O

Control

I/O

Control

I/O0R-I/O7R

(1,2)

BUSY

12R

12L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

(2)

INT ⁽²⁾

INTR

M/S

2683 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

MARCH 2018

DSC 2683/12

12 3 4 5 6 7...22

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