Model 636
5.0mm x 3.2mm Low Cost
HCMOS/TTL Clock Oscillator
ELECTRICAL CHARACTERISTICS
PARAMETER
Enable Function
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Enable Input Voltage
Model 636M
Model 636N
Model 636L
Model 636S
Pin 1 Logic '1', Output Enabled
Pin 1 Logic '1', Output Enabled
Pin 1 Logic '1', Output Enabled
Pin 1 Logic '1', Output Enabled
1.26
1.75
2.0
-
-
-
-
-
-
-
-
VIH
V
4.0
Disable Input Voltage
Model 636M,636N,636L
Model 636S
VIL
Pin 1 Logic '0', Output Disabled
Pin 1 Logic '0', Output Disabled
Pin 1 Logic '1'
-
-
-
-
-
-
-
-
0.3
0.8
10
TPLZ
IST
Enable Time (M,N,L,S)
Standby Current
ms
µA
Pin 1 Logic '0', Output Disabled
10
LVCMOS OUTPUT WAVEFORM
TEST CIRCUIT, CMOS LOAD
ENABLE TRUTH TABLE
PIN 1
Logic ‘1’
Open
PIN 3
Output
Output
Logic ‘0’
High Imp.
MECHANICAL SPECIFICATIONS
PACKAGE DRAWING
MARKING INFORMATION
1. ** - Manufacturing Site Code.
2. YWW – Date code, Y – year, WW – week.
3. XXXMXXXX – Frequency is marked with only
leading significant digits before the ‘M’ and 4 digits
after the ‘M’ [including zeros].
Ex. XXMXXXX [62M5000]
XXXMXXXX [155M5200]
CTS**YWW
● XXXMXXXX
NOTES
1. Termination pads [e4]. Barrier-plating is nickel [Ni]
with gold [Au] flash plate.
2. Reflow conditions per JEDEC J-STD-020, 260°C
maximum.
3. Moisture Sensitivity Level 1 per JEDEC J-STD-020.
D.U.T. PIN ASSIGNMENTS
PIN
SYMBOL
DESCRIPTION
SUGGESTED SOLDER PAD GEOMETRY
CBYPASS should be ≥ 0.01 uF.
1
EOH
Enable
2
GND
Circuit & Package Ground
RF Output
3
4
Output
VCC
Supply Voltage
Document No. 008-0250-0
Page 3 - 3
Rev. G