Model 635
7.0mm x 5.0mm Low Jitter
LVPECL or LVDS Clock
ELECTRICAL CHARACTERISTICS
PARAMETER
Maximum Supply Voltage
Storage Temperature
Frequency Range
LVPECL
SYMBOL
VCC
CONDITIONS
MIN
-0.5
-40
TYP
-
MAX
5.0
UNIT
V
-
TSTG
-
-
+100
°C
fO
Δf/fO
TA
-
MHz
± ppm
°C
10.00
-
-
-
-
320
LVDS
80.00
320
Frequency Stability
All Inclusive, see Note 1.
1st year aging
-
-
20, 25, 50, 100
3
Operating Temperature
Commercial
-
-20
-40
+70
+85
2.63
3.47
25
Industrial
Supply Voltage
2.38
3.14
2.5
3.3
VCC
± 5 %
V
Supply Current
LVPECL
ICC
Maximum Load
mA
ms
ps
-
-
-
-
-
-
-
-
88
65
5
LVDS
TS
Application of VCC
Start Up Time
2
Phase Jitter
tjrms
pjrms
Bandwidth 12 kHz - 20 MHz
0.3
2.6
25
0.7
-
Period Jitter RMS
Period Jitter Pk-Pk
Enable Function
Enable Input Voltage
Disable Input Voltage
Disable Time
-
-
-
Standby
VIH
VIL
0.7*VCC
V
Pin 1 or 2 Logic '1', Output Enabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '0' , Output Disabled
Pin 1 or 2 Logic '1', Output Enabled
-
-
-
-
-
0.3*VCC
200
-
-
-
TPLZ
TPLZ
ns
Enable Time
2
ms
LVPECL WAVEFORM
Output Load
RL
Terminated to VCC - 2.0V
@ VCC - 1.3V
-
50
-
-
Ohms
%
Output Duty Cycle
Output Voltage Levels
Logic '1' Level
SYM
45
55
VOH
VOL
VCC - 1.025
VCC - 1.810
VCC - 1.085
VCC - 1.830
-
VCC - 0.880
VCC - 1.620
VCC - 0.880
VCC - 1.555
0.7
PECL Load, -20°C to +70°C
PECL Load, -20°C to +70°C
PECL Load, -40°C to +85°C
PECL Load, -40°C to +85°C
@ 20% - 80% Levels
-
-
V
Logic '0' Level
VOH
Logic '1' Level
-
V
VOL
Logic '0' Level
-
TR, TF
Rise and Fall Time
LVDS WAVEFORM
Output Load
0.3
ns
RL
Between Outputs
@ 1.25V
-
100
-
-
Ohms
%
Output Duty Cycle
Differential Output Voltage
Offset Voltage
SYM
VOD
VOS
45
55
RL = 100 Ohms
LVDS Load
247
1.125
350
1.25
454
1.375
mV
V
Output Voltage Levels
Logic '1' Level
VOH
VOL
V
LVDS Load
-
0.90
-
1.43
1.10
0.4
1.60
-
Logic '0' Level
LVDS Load
TR, TF
Rise and Fall Time
Notes:
@ 20% - 80% Levels
0.7
ns
1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
LVPECL/LVDS OUTPUT WAVEFORM
ENABLE TRUTH TABLE
PIN 1 or Pin 2
Logic ‘1’
PIN 4 & 5
Output
Output
High Z
Open
Logic ‘0’
Document No. 008-0284-0
Page 2 - 3
Rev. E