Model 635
7.5x5.0mm Low Cost
LVPECL or LVDS Clock Oscillator
ELECTRICAL CHARACTERISTICS
PARAMETER
Maximum Supply Voltage
Storage Temperature
SYMBOL
VCC
TSTG
CONDITIONS
MIN
-0.5
-55
TYP
-
-
MAX
5.0
125
UNIT
V
°C
-
-
Frequency Range (See Note 1)
LVPECL and LVDS
fO
-
MHz
19.44
-
-
-
250
20, 25, 50
or 100
Frequency Stability
(See Note 2 and Ordering Information)
∆f/fO
-
± ppm
Operating Temperature
Commercial
Industrial
TA
VCC
ICC
-
°C
V
-20
-40
2.38
3.14
70
85
2.63
3.47
25
2.5
3.3
Supply Voltage
± 5 %
Supply Current
LVPECL
LVDS
Start Up Time
Phase Jitter
Period Jitter
Maximum Load
-
-
-
-
-
mA
50
25
3
-
-
100
60
5
1
5
TS
tjrms
pjrms
Application of VCC
ms
ps RMS
ps RMS
Bandwidth 12 kHz - 20 MHz
-
Enable Function
Enable Input Voltage
Disable Input Voltage
Disable Current
Enable Time
Standby
VIH
VIL
IIL
0.7*VCC
Pin 1 or Pin 2 Logic '1', Output Enabled
Pin 1 or Pin 2 Logic '0', Output Disabled
Pin 1 or Pin 2 Logic '1' , Output Disabled
Pin 1 or Pin 2 Logic '1'
-
-
-
-
-
0.3*VCC
20
V
-
-
-
uA
ns
TPLZ
5
LVPECL WAVEFORM
RL
SYM
-
-
45
50
-
-
55
Ohms
%
Output Load
@ VCC - 1.3V
Output Duty Cycle
Output Voltage Levels
Logic '1' Level
VOH
VOL
VCC - 1.025V
-
V
PECL Load
PECL Load
-
-
-
VCC - 1.62V
Logic '0' Level
Rise and Fall Time
fO < 100 MHz
fO > 100 MHz
TR, TF
@ 20% - 80% Levels
ns
-
-
0.8
0.5
1.0
0.6
LVDS WAVEFORM
RL
SYM
VOD
-
VOS
-
Between Outputs
@ 1.25V
RL = 100 Ohms
-
45
247
-
1.125
-
100
-
55
454
50
1.375
50
Ohms
%
mV
mV
V
Output Load
Output Duty Cycle
Differential Output Voltage
Differential Output Error
Offset Voltage
-
350
-
1.25
-
-
LVDS Load
-
Offset Error
mV
Output Voltage Levels
Logic '1' Level
Logic '0' Level
VOH
VOL
V
LVDS Load
LVDS Load
-
0.9
1.43
1.1
1.6
-
Rise and Fall Time
fO < 100 MHz
TR, TF
@ 20% - 80% Levels
ns
-
-
0.8
0.5
1.0
0.6
fO > 100 MHz
Notes:
1. For frequencies above 160 MHz consult factory for availability.
2. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 10 year aging.
PECL/LVDS OUTPUT WAVEFORM
Tr
Tf
VOH
VOS
OUT
80%
50%
20%
ENABLE TRUTH TABLE
PIN 1 or PIN 2 PIN 4 / PIN 5
OUT
Logic ‘1’
Open
Output
Output
VOL
UPTIME (t)
Logic ‘0’
High Imp.
PERIOD (T)
DUTY CYCLE = t/T x 100 (%)
Document No. 008-0284-0
Page 2 - 4
Rev. D
٠
٠
٠
CTS Electronic Components, Inc. ٠
171 Covington Drive ٠
Bloomingdale, IL 60108 ٠
٠
٠