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626

更新时间: 2023-12-06 20:13:37
品牌 Logo 应用领域
西迪斯 - CTS /
页数 文件大小 规格书
10页 2575K
描述
Leadless Castellated Ceramic

626 数据手册

 浏览型号626的Datasheet PDF文件第1页浏览型号626的Datasheet PDF文件第2页浏览型号626的Datasheet PDF文件第4页浏览型号626的Datasheet PDF文件第5页浏览型号626的Datasheet PDF文件第6页浏览型号626的Datasheet PDF文件第7页 
Model 626  
Very Low Jitter LVPECL or LVDS Clock  
Electrical Specifications  
Output Parameters  
PARAMETER  
SYMBOL  
TS  
CONDITIONS  
MIN  
-
TYP  
3
MAX  
10  
UNIT  
ms  
Start Up Time  
Application of VCC  
Enable Function [Standby]  
Enable Input Voltage  
Disable Input Voltage  
Disable Time  
VIH  
VIL  
Pin 1 Logic '1', Output Enabled  
Pin 1 Logic '0', Output Disabled  
0.7VCC  
-
-
0.3VCC  
200  
15  
V
V
-
-
-
-
-
-
-
TPLZ  
IST  
Pin 1 Logic '0', Output Disabled  
-
ns  
µA  
ms  
fs  
Standby Current  
Enable Time  
Pin 1 Logic '0', Output Disabled  
-
TPLZ  
Pin 1 Logic '1', Output Enabled  
-
300  
-
4
40MHz - 220MHz, Bandwidth 12kHz to 20MHz  
6MHz - 39.999MHz, Bandwidth 12kHz to 5MHz  
500  
<1  
Phase Jitter, RMS  
tjrms  
ps  
Enable Truth Table  
Pin 1  
Logic ‘1’  
Open  
Pin 4 & Pin 5  
Output Enabled  
Output Enabled  
Output Disabled,  
High Impedance  
Logic ‘0’  
Test Circuit  
LVPECL  
LVDS  
Output Waveform  
LVPECL or LVDS  
DOC# 008-0586-0 Rev. E  
Page 3 of 10  
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test  
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.  

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