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5CEFA9F27I7N

更新时间： 2024-02-12 17:36:46
品牌 Logo 应用领域
英特尔 - INTEL 时钟栅可编程逻辑
页数 文件大小 规格书
95页 1359K
描述
Field Programmable Gate Array, 301000 CLBs, 622MHz, 301000-Cell, CMOS, PBGA672, 27 MM, ROHS COMPLIANT, FBGA-672

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5CEFA9F27I7N 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：BGA包装说明：BGA, BGA672,26X26,40
针数：672Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：4.51
最大时钟频率：622 MHzJESD-30 代码：S-PBGA-B672
JESD-609代码：e1长度：27 mm
湿度敏感等级：3可配置逻辑块数量：301000
输入次数：336逻辑单元数量：301000
输出次数：336端子数量：672
组织：301000 CLBS封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA672,26X26,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.1,1.2/3.3,2.5 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：2 mm子类别：Field Programmable Gate Arrays
最大供电电压：1.13 V最小供电电压：1.07 V
标称供电电压：1.1 V表面贴装：YES
技术：CMOS端子面层：TIN SILVER COPPER
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：27 mmBase Number Matches：1

5CEFA9F27I7N 数据手册

 浏览型号5CEFA9F27I7N的Datasheet PDF文件第4页浏览型号5CEFA9F27I7N的Datasheet PDF文件第5页浏览型号5CEFA9F27I7N的Datasheet PDF文件第6页浏览型号5CEFA9F27I7N的Datasheet PDF文件第8页浏览型号5CEFA9F27I7N的Datasheet PDF文件第9页浏览型号5CEFA9F27I7N的Datasheet PDF文件第10页 
CV-51002  
2015.12.04  
7
Transceiver Power Supply Operating Conditions  
Symbol  
Description  
Condition  
Commercial  
Industrial  
Minimum(2)  
0
Typical  
—
Maximum(2)  
85  
Unit  
°C  
°C  
°C  
—
TJ  
Operating junction temperature  
–40  
—
100  
Automotive  
Standard POR  
Fast POR  
–40  
—
125  
200µs  
200µs  
—
100ms  
4ms  
(7)  
tRAMP  
Power supply ramp time  
—
—
Transceiver Power Supply Operating Conditions  
Table 4: Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices  
Symbol  
Description  
Minimum(8)  
2.375  
Typical  
2.5  
Maximum(8)  
Unit  
VCCH_GXBL  
Transceiver high voltage power (left side)  
Transmitter and receiver power (left side)  
Clock network power (left side)  
2.625  
V
V
V
(9)(10)  
VCCE_GXBL  
1.07/1.17  
1.07/1.17  
1.1/1.2  
1.1/1.2  
1.13/1.23  
1.13/1.23  
(9)(10)  
VCCL_GXBL  
(2)  
(7)  
(8)  
(9)  
The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.  
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.  
This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL = 0 and tRAMP  
specifications for fast POR when HPS_PORSEL = 1.  
The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.  
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.  
Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT and ST FPGA systems which  
require full compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended  
in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.  
Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specifica‐  
tion at 4.9152 Gbps ( Cyclone V GT and ST devices) and 6.144Gbps ( Cyclone V GT and ST devices only). For more information about the  
maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configura‐  
tions in Cyclone V Devices chapter.  
(10)  
Cyclone V Device Datasheet  
Send Feedback  
Altera Corporation  
1...45678910...95

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