Datasheet > 5AGXFA3G427I3ES

5AGXFA3G427I3ES

更新时间： 2022-04-17 03:12:22

品牌	Logo	应用领域
阿尔特拉 - ALTERA		/
页数	文件大小	规格书
37页	793K
描述
Arria V Device Overview

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5AGXFA3G427I3ES 数据手册

AV-51001

2013.05.06

Maximum Resources

Table 4: Maximum Resource Counts for Arria V GX Devices—Preliminary

Member Code

Resource

Logic Elements (LE)

(K)

156

190

242

300

362

420

504

ALM

28,302

58,900

71,698

91,680

113,208 136,880 158,491

190,240

760,960

24,140

2,906

113,208 235,600 286,792 366,720 452,832 547,520 633,964

M10K

MLAB

8,000

463

10,510

961

11,800

1,173

600

13,660

1,448

800

15,100

1,852

920

17,260

2,098

1,045

20,540

2,532

1,092

Memory

(Kb)

Variable-precision

DSP Block

240

396

1,156

18 x 18 Multiplier

PLL²

480

792

1,200

1,600

1,840

2,090

2,184

2,312

6 Gbps Transceiver

GPIO³

416

544

120

136

544

120

136

704

160

176

704

160

176

704

160

176

704

160

176

Transmitter

LVDS

Receiver

PCIe Hard IP Block

Hard Memory

Controller

Related Information

High-Speed Differential I/O Interfaces and DPA in Arria V Devices chapter, Arria V Device Handbook

Provides the number of LVDS channels in each device package.

The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs.

The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os

includes transceiver I/Os.

Arria V Device Overview

Altera Corporation

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