Datasheet > 5962-9669206HA

5962-9669206HA

更新时间： 2024-02-22 19:10:47

品牌	Logo	应用领域
MICROSS		内存集成电路
页数	文件大小	规格书
27页	1000K
描述
Flash, 512KX8, 55ns, CQCC32, CERAMIC, LCC-32

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5962-9669206HA 技术参数

生命周期：	Obsolete	零件包装代码：	QFJ
包装说明：	CERAMIC, LCC-32	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	3A001.A.2.C
HTS代码：	8542.32.00.51	风险等级：	5.82
最长访问时间：	55 ns	JESD-30 代码：	R-CQCC-N32
长度：	13.97 mm	内存密度：	4194304 bit
内存集成电路类型：	FLASH	内存宽度：	8
功能数量：	1	端子数量：	32
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	512KX8
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCN
封装形状：	RECTANGULAR	封装形式：	CHIP CARRIER
并行/串行：	PARALLEL	编程电压：	5 V
认证状态：	Not Qualified	筛选级别：	MIL-STD-883
座面最大高度：	2.032 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	QUAD
类型：	NOR TYPE	宽度：	11.43 mm
Base Number Matches：	1

5962-9669206HA 数据手册

FLASH

AS29F040

writing the reset command returns the device to reading array

data (also applies during Erase Suspend).

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the chip erase command, which

in turn invokes the Embedded Erase algorithm. The device

does not require the system to preprogram prior to erase. The

Embedded Erase algorithm automatically preprograms and

veriﬁes the entire memory for an all zero data pattern prior

to electrical erase. The system is not required to provide any

controls or timings during these operations. The Command

Deﬁnitions table shows the address and data requirements for

the chip erase command sequence.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes, and

determine whether or not a sector is protected. The Command

Deﬁnitions table shows the address and data requirements. This

method is an alternative to that shown in the Autoselect Codes

(High Voltage Method) table, which is intended for PROM

programmers and requires V_IDon address bit A9.

The auto select command sequence is initiated by writing

two unlock cycles, followed by the autoselect command. The

device then enters the autoselect mode, and the system may read

at any address any number of times, without initiating another

command sequence.

Aread cycle at address XX00h retrieves the manufacturer

code. A read cycle at address XX01h returns the device code.

A read cycle containing a sector address (SA) and the address

02h in returns 01h if that sector is protected, or 00h if it is un-

protected. Refer to the SectorAddress tables for valid sector

addresses.

Any commands written to the chip during the Embedded

Erase algorithm are ignored.

The system can determine the status of the erase

tion by using DQ7, DQ6, or DQ2. See “Write Operation Status”

for information on these status bits. When the Embedded

opera-

Erase algorithm is complete, the device returns to reading array

data and addresses are no longer latched.

Figure 2 illustrates the algorithm for the erase op-

eration. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and the Chip /Sector Erase

Operation Timings for timing waveforms.

The system must write the reset command to exit the au-

toselect mode and return to reading array data.

FIGURE 1: PROGRAM OPERATION

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two unlock

write cycles, followed by the program set-up command. The

program address and data are written next, which in turn initiate

the Embedded Program algorithm. The system is not required

to provide further controls or timings. The device

au-

tomatically provides internally generated program pulses and

verify the programmed cell margin. The Command Deﬁnitions

take shows the address and data requirements for the byte pro-

gram command sequence.

When the Embedded Program algorithm is complete, the

device then returns to reading array data and addresses are no

longer latched. The system can determine the status of the

program operation by using DQ7 or DQ6. See “Write Opera-

tion Status” for information on these status bits.

Any commands written to the device during the

bedded Program Algorithm are ignored.

Em-

Programming is allowed in any sequence and across sec-

tor boundaries. A bit cannot be programmed from a “0” back

to a “1”. Attempting to do so may halt the operation and set

DQ5 to “1”, or cause the Data\ Polling algorithm to indicate

the operation was successful. However, a succeeding read

will show that the data is still “0”. Only erase operations can

convert a “0” to a “1”.

NOTE: See the appropriate Command Deﬁnitions table for program com-

mand sequence.

Chip Erase Command Sequence

AS29F040

Micross Components reserves the right to change products or speciﬁcations without notice.

Rev. 2.3 01/10

1...4 5 678 9 10...27

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与5962-9669206HA相关器件

型号	品牌	获取价格	描述	数据表
5962-9669206HUA	MICROSS	获取价格	Flash, 512KX8, 55ns, FP-32
5962-9669401QVC	ETC	获取价格	x1 SRAM
5962-9669401QVX	WEDC	获取价格	IC 4K X 1 STANDARD SRAM, 250 ns, CDIP, Static RAM
5962-9669401QXC	ETC	获取价格	x1 SRAM
5962-9669501QVC	ETC	获取价格	x4 SRAM
5962-9669501QVX	WEDC	获取价格	Standard SRAM, 1KX4, 250ns, CMOS,
5962-9669501QXC	ETC	获取价格	x4 SRAM
5962-9669501QXX	WEDC	获取价格	IC 1K X 4 STANDARD SRAM, 250 ns, CDFP, Static RAM
5962-9669701QXA	ETC	获取价格	Bus Exchanger
5962-9669801QXA	ETC	获取价格	9-Bit Bus Transceiver

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