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5962-9322001QSA PDF预览

5962-9322001QSA

更新时间: 2024-02-19 19:39:14
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路输出元件信息通信管理
页数 文件大小 规格书
20页 761K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

5962-9322001QSA 技术参数

生命周期:Active零件包装代码:DFP
包装说明:CERAMIC, DFP-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.39Is Samacsys:N
其他特性:BROADSIDE VERSION OF 374系列:ABT
JESD-30 代码:R-GDFP-F20逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
传播延迟(tpd):7.4 ns认证状态:Qualified
筛选级别:MIL-PRF-38535 Class Q座面最大高度:2.286 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:MILITARY
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL宽度:6.731 mm
Base Number Matches:1

5962-9322001QSA 数据手册

 浏览型号5962-9322001QSA的Datasheet PDF文件第3页浏览型号5962-9322001QSA的Datasheet PDF文件第4页浏览型号5962-9322001QSA的Datasheet PDF文件第5页浏览型号5962-9322001QSA的Datasheet PDF文件第7页浏览型号5962-9322001QSA的Datasheet PDF文件第8页浏览型号5962-9322001QSA的Datasheet PDF文件第9页 
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ꢉꢊ ꢆꢄ ꢋ ꢌꢍ ꢎꢌꢏ ꢆꢐ ꢑꢎ ꢎꢌ ꢐꢌ ꢍ ꢍꢏꢆ ꢒ ꢓꢌ ꢔꢋ ꢑ ꢓꢏꢔ ꢋ ꢉ ꢓꢀ  
ꢕꢑ ꢆ ꢖ ꢗ ꢏꢀꢆꢄꢆ ꢌ ꢉꢘꢆ ꢓ ꢘꢆꢀ  
SCBS191F − JANUARY 1991 − REVISED SEPTEMBER 2003  
PARAMETER MEASUREMENT INFORMATION  
7 V  
TEST  
S1  
Open  
S1  
500 Ω  
From Output  
Under Test  
t
/t  
PLH PHL  
Open  
7 V  
GND  
t
/t  
PLZ PZL  
C
= 50 pF  
t
/t  
Open  
L
PHZ PZH  
500 Ω  
(see Note A)  
3 V  
0 V  
LOAD CIRCUIT  
Timing Input  
Data Input  
1.5 V  
t
w
t
t
h
su  
3 V  
0 V  
3 V  
0 V  
Input  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
3 V  
0 V  
3 V  
0 V  
Output  
Control  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
Input  
t
t
t
t
t
PZL  
PLZ  
PLH  
PHL  
PHL  
Output  
Waveform 1  
S1 at 7 V  
3.5 V  
V
V
OH  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
Output  
V
V
+ 0.3 V  
PHZ  
OL  
V
OL  
OL  
(see Note B)  
t
t
PZH  
t
PLH  
Output  
Waveform 2  
S1 at Open  
(see Note B)  
V
OH  
V
V
OH  
− 0.3 V  
OH  
1.5 V  
1.5 V  
Output  
0 V  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. includes probe and jig capacitance.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2.5 ns, t 2.5 ns.  
O
r
f
D. The outputs are measured one at a time with one transition per measurement.  
E. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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