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5962-9317709QNC

更新时间： 2024-01-21 22:35:06

品牌	Logo	应用领域
爱特美尔 - ATMEL		先进先出芯片
页数	文件大小	规格书
20页	2117K
描述
Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag

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数据手册

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5962-9317709QNC 数据手册

M672061H

Pin Description

Pin Name

I0 - 8

Q0 - 8

Description

Inputs

Outputs

Write Enable

Read Enable

Reset

Empty Flag

Full Flag

XO/HF

Expansion Out/Half-Full Flag

Expansion IN

First Load/Retransmit

Power Supply

Ground

FL/RT

VCC

GND

Data In (I₀- I₈)

Reset (RS)

Data inputs for 9-bit data

Reset occurs whenever the Reset (RS) input is taken to a low state. Reset returns both

internal read and write pointers to the first location. A reset is required after power-up

before a write operation can be enabled. Both the Read Enable (R) and Write Enable

(W) inputs must be in the high state during the period shown in Figure 2 (i.e. t_RSSbefore

the rising edge of RS) and should not change until tRSR after the rising edge of RS.

Otherwise, pulse write (or read) low during the reset operation loads the Programmable

Half Full Flag register from the data Inputs I0 - I8 (or data outputs Q0 - Q8) (shown in fig-

ure 2). In these two cases the Full Flag and the Programmable Half Full Flag are

reseted to high and the Empty Flag to low.

Figure 1. Reset (no write to Programmable Half Full Flag register)

Notes: 1. EF, FF and HF may change status during reset, but flags will be valid at t_RSC

2. W and R = VIH around the rising edge of RS.

4144K-AERO-04/07

1 234 5 6 7...20

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5962-9317709QTC	ATMEL	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag	获取价格
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5962-9317709VTC	ATMEL	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag	获取价格
5962-9317709VTX	ATMEL	FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28	获取价格
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