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5962-9211701M2A PDF预览

5962-9211701M2A

更新时间: 2024-01-06 07:55:28
品牌 Logo 应用领域
亚德诺 - ADI 运算放大器放大器电路
页数 文件大小 规格书
8页 338K
描述
High Speed, Low Power Dual Op Amp

5962-9211701M2A 技术参数

生命周期:Active零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.33.00.01风险等级:5.8
Is Samacsys:N放大器类型:OPERATIONAL AMPLIFIER
最大平均偏置电流 (IIB):7 µA标称共模抑制比:80 dB
最大输入失调电压:4000 µVJESD-30 代码:S-CQCC-N20
长度:8.89 mm负供电电压上限:-18 V
标称负供电电压 (Vsup):-15 V功能数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Qualified座面最大高度:2.54 mm
标称压摆率:300 V/us子类别:Operational Amplifier
供电电压上限:18 V标称供电电压 (Vsup):15 V
表面贴装:YES技术:BIPOLAR
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED标称均一增益带宽:50000 kHz
宽度:8.89 mmBase Number Matches:1

5962-9211701M2A 数据手册

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AD827  
multipliers connected in series. They could also be placed in  
parallel with an increase in bandwidth and a reduction in gain.  
The gain of the circuit is controlled by VX, which can range  
from 0 to 3 V dc. Measurements show that this circuit easily  
supplies 2 V p-p into a 100 load while operating from ±5 V  
supplies. The overall bandwidth of the circuit is approximately  
7 MHz with 0.5 dB of peaking.  
Current limiting in the AD827 (typically 30 mA) limits the out-  
put voltage in this application to about 3 V p-p across a 100 Ω  
load. Driving a 50 reverse-terminated load divides this value  
by two, limiting the maximum signal delivered to a 50 load to  
about 1.5 V p-p, which suffices for video signal levels. The  
dynamic range of this circuit is approximately 55 dB and is  
primarily limited by feedthrough at low input levels and by the  
maximum output voltage at high levels.  
Each half of the AD827 serves as an I/V converter and converts  
the output current of one of the two multipliers in the AD539  
into an output voltage. Each of the AD539’s two multipliers  
contains two internal 6 kfeedback resistors; one is connected  
between the CH1 output and Z1, the other between the CH1  
output and W1. Likewise, in the CH2 multiplier, one of the  
feedback resistors is connected between CH2 and Z2 and the  
other is connected between CH2 and Z2. In Figure 25, Z1 and  
W1 are tied together, as are Z2 and W2, providing a 3 kΩ  
feedback resistor for the op amp. The 2 pF capacitors connected  
between the AD539’s W1 and CH1 and W2 and CH2 pins are  
in parallel with the feedback resistors and thus reduce peaking  
in the VCA’s frequency response. Increasing the values of C3  
and C4 can further reduce the peaking at the expense of  
reduced bandwidth. The 1.25 mA full-scale output current of  
the AD539 and the 3 kfeedback resistor set the full-scale  
output voltage of each multiplier at 3.25 V p-p.  
Guidelines for Grounding and Bypassing  
When designing practical high frequency circuits using the  
AD827, some special precautions are in order. Both short  
interconnection leads and a large ground plane are needed  
whenever possible to provide low resistance, low inductance  
circuit paths. One should remember to minimize the effects of  
capacitive coupling between circuits. Furthermore, IC sockets  
should be avoided. Feedback resistors should be of a low  
enough value that the time constant formed with stray circuit  
capacitances at the amplifier summing junction will not limit  
circuit performance. As a rule of thumb, use feedback resistor  
values that are less than 5 k. If a larger resistor value is  
necessary, a small (<10 pF) feedback capacitor in parallel with  
the feedback resistor may be used. The use of 0.1 µF ceramic  
disc capacitors is recommended for bypassing the op amp’s  
power supply leads.  
OUTLINE DIMENSIONS  
Dimensions shown in inches and (mm).  
8-Pin Mini-DIP (N) Package  
8-Pin Cerdip (Q) Package  
16-Pin SOIC (R) Package  
20-Terminal Leadless Ceramic Chip Carrier  
(E-20A)  
–8–  
REV. B  

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