ATW2812S
TABLE II. Electrical Performance Characteristics - Continued.
Test
Symbol
Conditions
Group A
Subgroups
Device
Type
Limits
Unit
-55°C £ TC £ +125°C
IN = 28 V dc ±5%, CL = 0 unless
otherwise specified
V
Min
250
Max
Switching frequency
FS
IOUT = 6000 mA
4,5,6
01
02
03
All
300 kHz
270
250
275
300
Output response to step
transient load changes 8/
VOTLOAD
4000 mA to/from 6000 mA
4,5,6
-500
+500 mV pk
500 mA to/from 2500 mA
4000 mA to/from 6000 mA
4,5,6
4
All
All
-500
+500
Recovery time step transient
load changes 8/ 9/
TTLOAD
100 µs
5,6
4
200
500 mA to/from 2500 mA
All
100
5,6
200
Turn on overshoot
Turn on delay 10/
Load fault recovery 6/ 10/
Weight
VTonOS
TonD
IOUT = 0 and 6000 mA
IOUT = 0 and 6000 mA
4,5,6
4,5,6
4,5,6
All
All
All
500 mV pk
12 ms
12 ms
75 grams
TrLF
Flange
Notes:
1/ Parameter guaranteed by line and load regulation tests.
2/ Bandwidth guaranteed by design. Tested for 20 KHz to 2 MHz.
3/ Above +125°C case, derate output power linearly to 0 at +135°C.
4/ Output voltage measured at load with remote sense leads connected across load.
5/ Capacitive load may be any value from 0 to the maximum limit without compromising dc performance. A capacitive load in excess of the maximum limit
will not disturb loop stability but may interfere with the operation of the load fault detection circuitry, appearing as a short circuit during turn on.
6/ Parameter shall be tested as part of design characterization and after design or process changes. Thereafter parameters shall be guaranteed to the limits
specified in Table II.
7/ An overload is that condition with a load in excess of the rated load but less than that necessary to trigger the short circuit protection and is the condition of
maximum power dissipation.
8/ Load step transition time between 2 and 10 microseconds.
9/ Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1 percent of VOUT at 50 percent load.
10/ Turn on delay time measurement is for either a step application of power at the input or the removal of a ground signal from the inhibit pin (pin 2) while
power is applied to the input.
5