Datasheet > 5962-9052801MXA

5962-9052801MXA

更新时间： 2024-01-07 06:03:42

品牌	Logo	应用领域
超微 - AMD		接口集成电路
页数	文件大小	规格书
127页	704K
描述
TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)

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5962-9052801MXA 技术参数

生命周期：	Obsolete	包装说明：	DIP, DIP28,.6
Reach Compliance Code：	unknown	风险等级：	5.83
JESD-30 代码：	R-XDIP-T28	端子数量：	28
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC	封装代码：	DIP
封装等效代码：	DIP28,.6	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	5 V
认证状态：	Not Qualified	筛选级别：	38535Q/M;38534H;883B
子类别：	Other Telecom ICs	最大压摆率：	0.335 mA
标称供电电压：	5 V	表面贴装：	NO
技术：	TTL	温度等级：	MILITARY
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	Base Number Matches：	1

5962-9052801MXA 数据手册

FINAL

Advanced

Micro

Am7968/Am7969

TAXIchip^TMIntegrated Circuits

Devices

(Transparent Asynchronous Xmitter-Receiver Interface)

DISTINCTIVE CHARACTERISTICS

■ Parallel TTL bus interface

■ Easy interface with fiber optic data links

■ 32–140 Mbps (4–17.5 Mbyte/s) data

— Eight Data and four Command Pins

— or nine Data and three Command Pins

— or ten Data and two Command Pins

■ Transparent synchronous serial link

— +5 V ECL Serial I/O

throughput

■ Asynchronous input using STRB/ACK

■ Automatic MUX/DEMUX of Data and Command

■ Complete on-chip PLL, Crystal Oscillator

■ Single +5 V supply operation

— AC or DC coupled

■ 28-pin PLCC or DIP or LCC

— NRZI 4B/5B, 5B/6B encoding/decoding

■ Drive coaxial cable or twisted pair directly

GENERAL DESCRIPTION

The Am7968 TAXIchip Transmitter and Am7969

TAXIchip Receiver Chipset is a general-purpose inter-

face for very high-speed (4–17.5 Mbyte/s, 40–175

Mbaud serially) point-to-point communications over co-

axial or fiber-optic media. The TAXIchip set emulates a

pseudo-parallel register. They load data into one side

and output it on the other, except in this case, the “other”

side is separated by a long serial link.

The speed of a TAXIchip system is adjustable over a

range of frequencies, with parallel bus transfer rates of

4 Mbyte/s at the low end, and up to 17.5 Mbyte/s at the

high end. The flexible bus interface scheme of the

TAXIchip set accepts bytes that are either 8, 9, or

10 bits wide. Byte transfers can be Data or Command

signaling.

BLOCK DIAGRAM

Am7968

Data Command

Strobe &

Acknowledge

Strobe (STRB)

Acknowledge (ACK

Input Latch

Oscillator

and

Encoder Latch

Clock Gen.

Clock (CLK)

Data Encoder

Shifter

Data Mode Select (DMS)

(SEROUT+) Serial Out +

(SEROUT–) Serial Out –

Media

Interface

Test Serial In

Serial Interface

(TSERIN)

Test/Local Select (TLS)

07370F-1

Note:

N can be 8, 9, or 10 bits; total of N + M = 12.

Publication# 07370 Rev. F Amendment/0

Issue Date: April 1994

1 2 3 456 7 8...127

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