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5962-8973001LA PDF预览

5962-8973001LA

更新时间: 2024-11-20 14:46:47
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
7页 83K
描述
CDIP-24, Tube

5962-8973001LA 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:CDIP
包装说明:DIP, DIP24,.3针数:24
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.32Is Samacsys:N
其他特性:MASTER CONTROL FOR LATCH AND OUTPUT ENABLES IN EACH DIRECTION控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:FCT
JESD-30 代码:R-GDIP-T24JESD-609代码:e0
长度:32.004 mm负载电容(CL):50 pF
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER最大I(ol):0.048 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP24,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):240电源:5 V
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):14 ns
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:5.08 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:7.62 mmBase Number Matches:1

5962-8973001LA 数据手册

 浏览型号5962-8973001LA的Datasheet PDF文件第2页浏览型号5962-8973001LA的Datasheet PDF文件第3页浏览型号5962-8973001LA的Datasheet PDF文件第4页浏览型号5962-8973001LA的Datasheet PDF文件第5页浏览型号5962-8973001LA的Datasheet PDF文件第6页浏览型号5962-8973001LA的Datasheet PDF文件第7页 
FAST CMOS  
OCTAL LATCHED  
TRANSCEIVER  
IDT54/74FCT543/A/C  
FEATURES:  
DESCRIPTION:  
• IDT54FCT543 equivalent to FAST™ speed  
TheFCT543isanon-invertingoctaltransceiverbuiltusinganadvanced  
dual metal CMOS technology. These devices contain two sets of eight D-  
type latches with separate input and output controls for each set. For data  
flow from A to B, for example, the A-to-B Enable (CEAB) input must be low  
in order to enter data from A0–A7 or to take data from B0–B7, as indicated  
in the Function Table. With CEAB low, a low signal on the A-to-B Latch  
Enable(LEAB)inputmakestheA-to-Blatchestransparent;a subsequent  
low-to-high transition of the LEAB signal puts the A latches in the storage  
modeandtheiroutputsnolongerchangewiththeAinputs. WithCEABand  
OEAB both low, the 3-state B output buffers are active and reflect the data  
presentattheoutputoftheAlatches. ControlofdatafromBtoAissimilar,  
but uses the CEBA, LEBA and OEBA inputs.  
• IDT54/74FCT543A up to 25% faster than FAST  
• IDT74FCT543C up to 40% faster than FAST  
• Eqivalent to FAST output drive over full temperature and voltage  
supply extremes  
• IOL = 64mA (commercial) and 48mA (military)  
• Separate controls for data flow in each direction  
• Back-to-back latches for storage  
• CMOS power levels (1mW typ. static)  
• Substantially lower input current levels than FAST (5µA max.)  
• TTL input and output level compatible  
• CMOS output level compatible  
• MIlitary product compliant to MIL-STD-883, Class B  
• Available in the following packages:  
– Commercial: SOIC  
– Military: CERDIP, LCC  
FUNCTIONALBLOCKDIAGRAM  
DETAIL A  
22  
Q
D
B0  
LE  
3
Q
D
A0  
LE  
4
5
21  
20  
19  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
B1  
B2  
B3  
6
7
DETAIL A x 7  
18  
17  
16  
15  
B4  
B5  
B6  
B7  
8
9
10  
2
OEBA  
13  
OEAB  
23  
1
CEBA  
LEBA  
11  
14  
CEAB  
LEAB  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 2003  
1
© 2003 Integrated Device Technology, Inc.  
DSC-4602/7  

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