Datasheet > 逻辑 > 栅极> 5962-8869301RA

5962-8869301RA

更新时间： 2024-01-26 15:18:22

品牌	Logo	应用领域
德州仪器 - TI		输入元件驱动
页数	文件大小	规格书
13页	437K
描述
HEX 2-INPUT NAND DRIVERS

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

5962-8869301RA 技术参数

生命周期：	Active	零件包装代码：	DFP
包装说明：	DFP,	针数：	20
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.52	系列：	ALS
JESD-30 代码：	R-GDFP-F20	JESD-609代码：	e0
逻辑集成电路类型：	NAND GATE	功能数量：	6
输入次数：	2	端子数量：	20
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK
传播延迟（tpd）：	9 ns	认证状态：	Qualified
筛选级别：	MIL-STD-883	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	TTL
温度等级：	MILITARY	端子面层：	TIN LEAD
端子形式：	FLAT	端子位置：	DUAL
Base Number Matches：	1

5962-8869301RA 数据手册

SN54ALS804A, SN54AS804B, SN74ALS804A, SN74AS804B

HEX 2-INPUT NAND DRIVERS

SDAS022C – DECEMBER 1982 – REVISED JANUARY 1995

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

7 V

= R1 = R2

Test

Point

From Output

Under Test

From Output

Under Test

Test

Point

Test

Point

From Output

Under Test

(see Note A)

LOAD CIRCUIT FOR

BI-STATE

TOTEM-POLE OUTPUTS

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

3.5 V

Timing

Input

High-Level

1.3 V

Pulse

0.3 V

3.5 V

0.3 V

Data

Input

Low-Level

1.3 V

Pulse

0.3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATIONS

3.5 V

0.3 V

Output

Control

(low-level

enabling)

1.3 V

3.5 V

PZL

Input

1.3 V

PLZ

0.3 V

PHL

3.5 V

Waveform 1

S1 Closed

(see Note B)

PLH

1.3 V

In-Phase

Output

1.3 V

0.3 V

PHZ

PLH

PZH

PHL

Waveform 2

S1 Open

(see Note B)

Out-of-Phase

Output

(see Note C)

1.3 V

0.3 V

0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A.

C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. When measuring propagation delay items of 3-state outputs, switch S1 is open.

D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.

E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1 2 3 456 7 8...13

下载PDF

与5962-8869301RA相关器件

型号	品牌	描述	获取价格	数据表
5962-8869301RX	ETC	Hex 2-input NAND Gate	获取价格
5962-8869301SA	ETC	Hex 2-input NAND Gate	获取价格
5962-8869301SX	ETC	Hex 2-input NAND Gate	获取价格
5962-88694012A	ETC	Hex 2-input NOR Gate	获取价格
5962-88694012X	ETC	Hex 2-input NOR Gate	获取价格
5962-8869401RA	ETC	Hex 2-input NOR Gate	获取价格