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5962-8852514ZX PDF预览

5962-8852514ZX

更新时间： 2024-02-08 17:11:02
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器内存集成电路
页数 文件大小 规格书
25页 659K
描述
EEPROM, 32KX8, 150ns, Parallel, CMOS, CDFP28

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5962-8852514ZX 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：28
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.32.00.51风险等级：5.29
最长访问时间：150 nsJESD-30 代码：R-CDFP-F28
内存密度：262144 bit内存集成电路类型：EEPROM
内存宽度：8功能数量：1
端子数量：28字数：32768 words
字数代码：32000工作模式：ASYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：32KX8封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK并行/串行：PARALLEL
编程电压：5 V认证状态：Not Qualified
筛选级别：MIL-STD-883最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子位置：DUAL最长写入周期时间 (tWC)：10 ms
Base Number Matches：1

5962-8852514ZX 数据手册

 浏览型号5962-8852514ZX的Datasheet PDF文件第1页浏览型号5962-8852514ZX的Datasheet PDF文件第2页浏览型号5962-8852514ZX的Datasheet PDF文件第4页浏览型号5962-8852514ZX的Datasheet PDF文件第5页浏览型号5962-8852514ZX的Datasheet PDF文件第6页浏览型号5962-8852514ZX的Datasheet PDF文件第7页 
AT28C256  
3. Block Diagram  
4. Device Operation  
4.1  
Read  
The AT28C256 is accessed like a Static RAM. When CE and OE are low and WE is high, the  
data stored at the memory location determined by the address pins is asserted on the outputs.  
The outputs are put in the high impedance state when either CE or OE is high. This dual-line  
control gives designers flexibility in preventing bus contention in their system.  
4.2  
Byte Write  
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write  
cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is  
latched by the first rising edge of CE or WE. Once a byte write has been started it will automati-  
cally time itself to completion. Once a programming operation has been initiated and for the  
duration of tWC, a read operation will effectively be a polling operation.  
4.3  
Page Write  
The page write operation of the AT28C256 allows 1 to 64 bytes of data to be written into the  
device during a single internal programming period. A page write operation is initiated in the  
same manner as a byte write; the first byte written can then be followed by 1 to 63 additional  
bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC  
limit is exceeded the AT28C256 will cease accepting data and commence the internal program-  
ming operation. All bytes during a page write operation must reside on the same page as  
defined by the state of the A6 - A14 inputs. For each WE high to low transition during the page  
write operation, A6 - A14 must be the same.  
The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes  
may be loaded in any order and may be altered within the same load period. Only bytes which  
are specified for writing will be written; unnecessary cycling of other bytes within the page does  
not occur.  
4.4  
DATA Polling  
The AT28C256 features DATA Polling to indicate the end of a write cycle. During a byte or page  
write cycle an attempted read of the last byte written will result in the complement of the written  
data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all  
outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write  
cycle.  
3
0006M–PEEPR–12/09  
1234567...25

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