5962-87700022A

更新时间： 2024-01-19 09:40:04

品牌	Logo	应用领域
亚德诺 - ADI		转换器数模转换器
页数	文件大小	规格书
8页	164K
描述
CMOS 8-Bit Buffered Multiplying DAC

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技术参数
数据手册

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5962-87700022A 技术参数

生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	QCCN,	针数：	20
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.39.00.01	风险等级：	5.83
Is Samacsys：	N	转换器类型：	D/A CONVERTER
输入位码：	BINARY, OFFSET BINARY	输入格式：	PARALLEL, 8 BITS
JESD-30 代码：	S-CQCC-N20	最大线性误差 (EL)：	1.9531%
位数：	8	功能数量：	1
端子数量：	20	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	QCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER	认证状态：	Not Qualified
筛选级别：	MIL-STD-883	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	NO LEAD
端子位置：	QUAD	Base Number Matches：	1

5962-87700022A 数据手册

AD7524

WRITE MO D E

CIRCUIT D ESCRIP TIO N

When CS and WR are both LOW, the AD7524 is in the

WRIT E mode, and the AD7524 analog output responds to data

activity at the DB0–DB7 data bus inputs. In this mode, the

AD7524 acts like a nonlatched input D/A converter.

CIRCUIT INFO RMATIO N

T he AD7524, an 8-bit multiplying D/A converter, consists of a

highly stable thin film R-2R ladder and eight N-channel current

switches on a monolithic chip. Most applications require the

addition of only an output operational amplifier and a voltage

or current reference.

H O LD MO D E

When either CS or WR is HIGH, the AD7524 is in the HOLD

mode. T he AD7524 analog output holds the value correspond-

ing to the last digital input present at DB0–DB7 prior to WR or

CS assuming the HIGH state.

T he simplified D/A circuit is shown in Figure 1. An inverted

R-2R ladder structure is used—that is, the binarily weighted

currents are switched between the OUT 1 and OUT 2 bus lines,

thus maintaining a constant current in each ladder leg indepen-

dent of the switch state.

MO D E SELECTIO N TABLE

Mode

D AC Response

Write

DAC responds to data bus

(DB0–DB7) inputs.

Hold

Data bus (DB0–DB7) is

Locked Out:

DAC holds last data present

when WR or CS assumed

HIGH state.

L = Low State, H = High State, X = Don't Care.

WRITE CYCLE TIMING D IAGRAM

Figure 1. Functional Diagram

EQ UIVALENT CIRCUIT ANALYSIS

T he equivalent circuit for all digital inputs LOW is shown in

Figures 2. In Figure 2 with all digital inputs LOW, the refer-

ence current is switched to OUT 2. T he current source I_LEAKAGE

is composed of surface and junction leakages to the substrate

while the

current source represents a constant 1-bit cur-

256

rent drain through the termination resistor on the R-2R ladder.

T he “ON” capacitance of the output N-channel switches is

120 pF, as shown on the OUT 2 terminal. T he “OFF” switch

capacitance is 30 pF, as shown on the OUT 1 terminal. Analysis

of the circuit for all digital inputs high is similar to Figure 2

however, the “ON” switches are now on terminal OUT 1, hence

the 120 pF appears at that terminal.

Figure 2. AD7524 DAC Equivalent Circuit—All Digital

Inputs Low

INTERFACE LO GIC INFO RMATIO N

MO D E SELECTIO N

AD7524 mode selection is controlled by the CS and WR inputs.

Figure 3. Supply Current vs. Logic Level

T ypical plots of supply current, I_DD, versus logic input voltage,

_IN, for V_DD= +5 V and V_DD= +15 V are shown above.

–4–

REV. B

1 2 345 6 7 8

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型号	品牌	描述	获取价格	数据表
5962-87700022C	ETC	8-Bit Digital-to-Analog Converter	获取价格
5962-87700022X	ETC	8-Bit Digital-to-Analog Converter	获取价格
5962-8770002EA	ADI	CMOS 8-Bit Buffered Multiplying DAC	获取价格
5962-8770002EB	ETC	8-Bit Digital-to-Analog Converter	获取价格
5962-8770002EX	ETC	8-Bit Digital-to-Analog Converter	获取价格
5962-87700032A	ADI	CMOS 8-Bit Buffered Multiplying DAC	获取价格

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