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5962-8763101VRX PDF预览

5962-8763101VRX

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德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路输出元件
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5962-8763101VRX 数据手册

 浏览型号5962-8763101VRX的Datasheet PDF文件第2页浏览型号5962-8763101VRX的Datasheet PDF文件第3页浏览型号5962-8763101VRX的Datasheet PDF文件第4页浏览型号5962-8763101VRX的Datasheet PDF文件第5页浏览型号5962-8763101VRX的Datasheet PDF文件第6页浏览型号5962-8763101VRX的Datasheet PDF文件第7页 
SN54ACT374, SN74ACT374  
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCAS539F – OCTOBER 1995 – REVISED NOVEMBER 2002  
SN54ACT374 . . . J OR W PACKAGE  
SN74ACT374 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
4.5-V to 5.5-V V  
Operation  
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 10 ns at 5 V  
pd  
Inputs Are TTL-Voltage Compatible  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
CLK  
description/ordering information  
These 8-bit flip-flops feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The devices  
are particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND  
The eight flip-flops of the ’ACT374 devices are  
D-type edge-triggered flip-flops. On the positive  
transition of the clock (CLK) input, the Q outputs  
are set to the logic levels set up at the data (D)  
inputs.  
SN54ACT374 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
the increased drive provide the capability to drive  
bus lines in bus-organized systems without need  
for interface or pullup components.  
3
2 1 20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
4
5
6
7
8
17  
16  
15  
14 6D  
9 10 11 12 13  
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
Tube  
SN74ACT374N  
SN74ACT374N  
Tube  
SN74ACT374DW  
SN74ACT374DWR  
SN74ACT374NSR  
SN74ACT374DBR  
SN74ACT374PWR  
SNJ54ACT374J  
SOIC – DW  
ACT374  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
–40°C to 85°C  
SOP – NS  
SSOP – DB  
TSSOP – PW  
CDIP – J  
ACT374  
AD374  
AD374  
SNJ54ACT374J  
SNJ54ACT374W  
SNJ54ACT374FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54ACT374W  
SNJ54ACT374FK  
LCCC – FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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