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5962-8752501MDA PDF预览

5962-8752501MDA

更新时间: 2024-02-22 07:52:26
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路
页数 文件大小 规格书
16页 529K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

5962-8752501MDA 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP, FL14,.3针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.1系列:ACT
JESD-30 代码:R-GDFP-F14JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:85000000 Hz最大I(ol):0.024 A
位数:1功能数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL14,.3封装形状:RECTANGULAR
封装形式:FLATPACK电源:5 V
传播延迟(tpd):14 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535座面最大高度:2.032 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:6.2865 mm最小 fmax:95 MHz
Base Number Matches:1

5962-8752501MDA 数据手册

 浏览型号5962-8752501MDA的Datasheet PDF文件第2页浏览型号5962-8752501MDA的Datasheet PDF文件第3页浏览型号5962-8752501MDA的Datasheet PDF文件第4页浏览型号5962-8752501MDA的Datasheet PDF文件第6页浏览型号5962-8752501MDA的Datasheet PDF文件第7页浏览型号5962-8752501MDA的Datasheet PDF文件第8页 
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢃ ꢈ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢇ ꢃ  
ꢉꢊꢄ ꢋ ꢌꢍ ꢀꢎ ꢆ ꢎꢏꢐ ꢑꢐꢉꢒ ꢐꢑꢆ ꢓꢎ ꢒ ꢒꢐ ꢓꢐꢉ ꢉꢑꢆ ꢔꢌ ꢐ ꢕ ꢋ ꢎꢌ ꢑ ꢕꢋꢍ ꢌ ꢀ  
ꢖ ꢎꢆ ꢗ ꢅꢋ ꢐꢄꢓ ꢄꢁꢉ ꢌ ꢓꢐ ꢀ ꢐꢆ  
SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003  
switching characteristics over recommended operating free-air temperature (unless otherwise  
noted) (see Figure 1)  
SN74ACT74  
FROM  
(INPUT)  
TO  
(OUTPUT)  
T
A
= 25°C  
TYP  
210  
5.5  
6
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
145  
3
MAX  
f
t
t
t
t
125  
2.5  
3
MHz  
ns  
max  
PLH  
PHL  
PLH  
PHL  
9.5  
10  
11  
10.5  
11.5  
13  
PRE or CLR  
CLK  
Q or Q  
Q or Q  
3
4
7.5  
6
4
ns  
3.5  
10  
3
11.5  
operating characteristics, V  
= 5 V, T = 25°C  
A
CC  
PARAMETER  
TEST CONDITIONS  
TYP  
UNIT  
C
Power dissipation capacitance  
C
= 50 pF,  
f = 1 MHz  
45  
pF  
pd  
L
PARAMETER MEASUREMENT INFORMATION  
2 × V  
CC  
S1  
Open  
500 Ω  
From Output  
Under Test  
TEST  
S1  
C
= 50 pF  
L
t
/t  
Open  
PLH PHL  
500 Ω  
(see Note A)  
t
w
LOAD CIRCUIT  
1.5 V  
3 V  
0 V  
1.5 V  
1.5 V  
Input  
3 V  
0 V  
Input  
1.5 V  
VOLTAGE WAVEFORMS  
t
t
t
PHL  
PLH  
V
OH  
3 V  
In-Phase  
Output  
50% V  
50% V  
CC  
CC  
Timing Input  
Data Input  
1.5 V  
V
OL  
0 V  
t
h
t
PHL  
PLH  
t
su  
V
OH  
3 V  
0 V  
Out-of-Phase  
Output  
50% V  
50% V  
1.5 V  
1.5 V  
CC  
CC  
V
OL  
VOLTAGE WAVEFORMS  
NOTES: A. C includes probe and jig capacitance.  
VOLTAGE WAVEFORMS  
L
B. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, Z = 50 , t 2.5 ns, t 2.5 ns.  
C. The outputs are measured one at a time with one input transition per measurement.  
O
r
f
Figure 1. Load Circuit and Voltage Waveforms  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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