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5962-0250101QXC PDF预览

5962-0250101QXC

更新时间: 2023-02-26 13:36:33
品牌 Logo 应用领域
爱特美尔 - ATMEL 静态存储器
页数 文件大小 规格书
14页 1222K
描述
128K X 8 STANDARD SRAM, 40 ns, DFP32, 0.400 INCH, DFP-32

5962-0250101QXC 数据手册

 浏览型号5962-0250101QXC的Datasheet PDF文件第3页浏览型号5962-0250101QXC的Datasheet PDF文件第4页浏览型号5962-0250101QXC的Datasheet PDF文件第5页浏览型号5962-0250101QXC的Datasheet PDF文件第7页浏览型号5962-0250101QXC的Datasheet PDF文件第8页浏览型号5962-0250101QXC的Datasheet PDF文件第9页 
M65609E  
Write Cycle  
Symbol  
tAVAW  
Parameter  
65609E-40  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Value  
min  
min  
min  
min  
min  
min  
max  
min  
Write cycle time  
35  
0
tAVWL  
Address set-up time  
Address valid to end of write  
Data set-up time  
tAVWH  
28  
18  
28  
28  
15  
28  
tDVWH  
tE1LWH  
CS1 low to write end  
CS2 high to write end  
Write low to high Z (1)  
Write pulse width  
tE2HWH  
tWLQZ  
tWLWH  
Address hold from to end of  
write  
tWHAX  
3
ns  
min  
tWHDX  
tWHQX  
Data hold time  
0
0
ns  
ns  
min  
min  
Write high to low Z (1)  
Note:  
1. Parameters guaranteed, not tested, with 5 pF output loading (see Section “AC Test Conditions” Figure 2).  
Read Cycle  
Symbol  
tAVAV  
Parameter  
65609E-40  
Unit  
ns  
Value  
min  
Read cycle time  
Address access time  
Address valid to low Z  
40  
40  
3
tAVQV  
ns  
max  
min  
tAVQX  
ns  
Chip-select1 access  
time  
tE1LQV  
40  
ns  
max  
tE1LQX  
tE1HQZ  
CS1 low to low Z (1)  
CS1 high to high Z (1)  
3
ns  
ns  
min  
15  
max  
Chip-select2 access  
time  
tE2HQV  
40  
ns  
max  
tE2HQX  
tE2LQZ  
CS2 high to low Z (1)  
CS2 low to high Z (1)  
3
ns  
ns  
min  
15  
max  
Output Enable access  
time  
tGLQV  
12  
ns  
max  
tGLQX  
tGHQZ  
OE low to low Z (1)  
OE high to high Z (1)  
0
ns  
ns  
min  
10  
max  
Note:  
1. Parameters guaranteed, not tested, with 5 pF output loading (seeSection “AC Test Conditions” Figure 2).  
6
4158I–AERO–07/07  

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