Datasheet > 56F8135

56F8135

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		控制器
页数	文件大小	规格书
160页	2245K
描述
16-bit Digital Signal Controller

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数据手册

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56F8135 数据手册

56F8335/56F8135 Features

Part 1 Overview

1.1 56F8335/56F8135 Features

1.1.1

Core

•

Efficient 16-bit 56800E family controller engine with dual Harvard architecture

Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency

Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

Four 36-bit accumulators, including extension bits

Arithmetic and logic multi-bit shifter

Parallel instruction set with unique DSP addressing modes

Hardware DO and REP loops

Three internal address buses

Four internal data buses

Instruction set supports both DSP and controller functions

Controller-style addressing modes and instructions for compact code

Efficient C compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/EOnCE debug programming interface

1.1.2

Differences Between Devices

Table 1-1 outlines the key differences between the 56F8335 and 56F8135 devices.

Table 1-1 Device Differences

Feature

56F8335

56F8135

Guaranteed Speed

Program RAM

Data Flash

60MHz/60 MIPS

40MHz/40MIPS

Not Available

1 x 6

4KB

8KB

2 x 6

PWM

CAN

Not Available

Quad Timer

Quadrature Decoder

Temperature Sensor

2 x 4

1 x 4

Not Available

56F8335 Technical Data, Rev. 5

Freescale Semiconductor

Preliminary

1 2 3 456 7 8...160

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