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56F807 General Description

•

Up to 40 MIPS at 80MHz core frequency

•

Two 6 channel PWM Modules

DSP and MCU functionality in a unified,

C-efficient architecture

Four 4 channel, 12-bit ADCs

Two Quadrature Decoders

•

Hardware DO and REP loops

CAN 2.0 B Module

MCU-friendly instruction set supports both DSP

and controller functions: MAC, bit manipulation

unit, 14 addressing modes

Two Serial Communication Interfaces (SCIs)

Serial Peripheral Interface (SPI)

Up to four General Purpose Quad Timers

JTAG/OnCE^TMport for debugging

14 Dedicated and 18 Shared GPIO lines

160-pin LQFP or 160 MAPBGA Packages

•

60K × 16-bit words (120KB) Program Flash

2K × 16-bit words (4KB) Program RAM

8K × 16-bit words (16KB) Data Flash

4K × 16-bit words (8KB) Data RAM

2K × 16-bit words (4KB) Boot Flash

Up to 64K × 16- bit words (128KB) each of external

Program and Data memory

6

PWM Outputs

PWMA

PWMB

RSTO

EXTBOOT

IRQB

Current Sense Inputs

Fault Inputs

3

4

RESET

IRQA

VPP VCAPC

2

V

SSA

DD

SS

DDA

6

PWM Outputs

8

10*

3

Current Sense Inputs

Fault Inputs

3

4

JTAG/

OnCE

Port

Digital Reg

Analog Reg

A/D1

A/D2

ADCA

Low Voltage

Supervisor

VREF

A/D1

A/D2

ADCB

4

VREF2

Interrupt

Controller

Data ALU

Address

Generation

Unit

Bit

Manipulation

Unit

Program Controller

and

Hardware Looping Unit

Quadrature

Decoder 0

/Quad Timer

16 x 16 + 36 → 36-Bit MAC

Three 16-bit Input Registers

Two 36-bit Accumulators

4

Quadrature

Decoder 1

/Quad Timer B

Program Memory

61440 x 16 Flash

2048 x 16 SRAM

PAB

PLL

CLKO

4

2

•

PDB

16-Bit

56800

Core

•

Quad Timer C

XTAL

Boot Flash

2048 x 16 Flash

Clock Gen

Quad Timer D

/ Alt Func

EXTAL

XDB2

4

2

CGDB

Data Memory

8192 x 16 Flash

4096 x 16 SRAM

CAN 2.0A/B

•

XAB1

SCI0

or

GPIO

XAB2

•

INTERRUPT

CONTROLS

IPBB

CONTROLS

16

2

A[00:05]

SCI1

or

GPIO

External

Address Bus

Switch

16

6

A[06:15] or

GPIO-E2:E3 &

GPIO-A0:A7

COP/

Watchdog

COP RESET

External

Bus

Interface

Unit

10

16

External

Data Bus

Switch

MODULE CONTROLS

Applica-

tion-Specific

Memory &

Peripherals

SPI

or

GPIO

D[00:15]

IPBus Bridge

(IPBB)

ADDRESS BUS [8:0]

DATA BUS [15:0]

PS Select

DS Select

WR Enable

RD Enable

4

Bus

Control

Dedicated

GPIO

14

*includes TCS pin which is reserved for factory use and is tied to VSS

56F807 Block Diagram

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

3

Part 1 Overview

1.1 56F807 Features

1.1.1

Processing Core

•

Efficient 16-bit 56800 family controller engine with dual Harvard architecture

As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

Two 36-bit accumulators including extension bits

16-bit bidirectional barrel shifter

Parallel instruction set with unique processor addressing modes

Hardware DO and REP loops

Three internal address buses and one external address bus

Four internal data buses and one external data bus

Instruction set supports both DSP and controller functions

Controller style addressing modes and instructions for compact code

Efficient C compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/OnCE debug programming interface

1.1.2

Memory

•

Harvard architecture permits as many as three simultaneous accesses to Program and Data memory

On-chip memory including a low-cost, high-volume Flash solution

— 60K × 16-bit words of Program Flash

•

— 2K × 16-bit words of Program RAM

— 8K × 16-bit words of Data Flash

— 4K × 16-bit words of Data RAM

— 2K × 16-bit words of Boot Flash

•

Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states

— As much as 64K × 16 bits of Data memory

— As much as 64K × 16 bits of Program memory

1.1.3

Peripheral Circuits for 56F807

•

Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four

Fault inputs, fault tolerant design with dead time insertion, supports both center- and edge-aligned modes

•

Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with

quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized

Two Quadrature Decoders each with four inputs or two additional Quad Timers

56F807 Technical Data Technical Data, Rev. 15

4

Freescale Semiconductor

56F807 Description

•

Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with

four pins

•

CAN 2.0 B Module with 2-pin port for transmit and receive

Two Serial Communication Interfaces each with two pins (or four additional GPIO lines)

Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)

Computer-Operating Properly (COP) Watchdog timer

Two dedicated external interrupt pins

14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins

External reset input pin for hardware reset

External reset output pin for system reset

JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging

Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock

1.1.4

Energy Information

•

Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

Uses a single 3.3V power supply

On-chip regulators for digital and analog circuitry to lower cost and reduce noise

Wait and Stop modes available

1.2 56F807 Description

The 56F807 is a member of the 56800 core-based family of processors. It combines, on a single chip, the

processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to

create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact

program code, the 56F807 is well-suited for many applications. The 56F807 includes many peripherals

that are especially useful for applications such as motion control, smart appliances, steppers, encoders,

tachometers, limit switches, power supply and control, automotive control, engine management, noise

suppression, remote utility metering, industrial control for power, lighting, and automation.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and

optimized instruction set allow straightforward generation of efficient, compact DSP and control code.

The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized

control applications.

The 56F807 supports program execution from either internal or external memories. Two data operands can

be accessed from the on-chip Data RAM per instruction cycle. The 56F807 also provides two external

dedicated interrupt lines and up to 32 General Purpose Input/Output (GPIO) lines, depending on peripheral

configuration.

The 56F807 controller includes 60K, 16-bit words of Program Flash and 8K words of Data Flash (each

programmable through the JTAG port) with 2K words of Program RAM and 4K words of Data RAM. It

also supports program execution from external memory.

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

5

A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable

software routines that can be used to program the main Program and Data Flash memory areas. Both

Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words.

The Boot Flash memory can also be either bulk or page erased.

A key application-specific feature of the 56F807 is the inclusion of two Pulse Width Modulator (PWM)

modules. These modules each incorporate three complementary, individually programmable PWM signal

outputs (each module is also capable of supporting six independent PWM functions, for a total of 12 PWM

outputs) to enhance motor control functionality. Complementary operation permits programmable dead

time insertion, distortion correction via current sensing by software, and separate top and bottom output

polarity control. The up-counter value is programmable to support a continuously variable PWM

frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is

supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both

BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance

Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting

with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”,

write-once protection feature for key parameters is also included. A patented PWM waveform distortion

correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit

integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output to

synchronize the analog-to-digital converters.

The 56F807 incorporates two separate Quadrature Decoders capable of capturing all four transitions on

the two-phase inputs, permitting generation of a number proportional to actual position. Speed

computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer

in the Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is

detected. Each input is filtered to ensure only true transitions are recorded.

This controller also provides a full set of standard programmable peripherals that include two Serial

Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of

these interfaces can be used as General-Purpose Input/Outputs (GPIO) if that function is not required. A

Controller Area Network interface (CAN Version 2.0 A/B-compliant), an internal interrupt controller, and

14 dedicated GPIO lines are also included on the 56F807.

1.3 State of the Art Development Environment

•

Processor Expert^TM(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use

component-based software application creation with an expert knowledge system.

•

The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,

compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards

will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable

tools solution for easy, fast, and efficient development.

56F807 Technical Data Technical Data, Rev. 15

6

Freescale Semiconductor

Product Documentation

1.4 Product Documentation

The four documents listed in Table 1-1 are required for a complete description and proper design with the

56F807. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices,

Freescale Literature Distribution Centers, or online at http://www.freescale.com

.

Table 1-1 56F807 Chip Documentation

Topic

Description

Order Number

56800EFM

56800E

Detailed description of the 56800 family architecture,

and 16-bit core processor and the instruction set

Family Manual

DSP56F801/803/805/807

User’s Manual

Detailed description of memory, peripherals, and

interfaces of the 56F801, 56F803, 56F805, and

56F807

DSP56F801-7UM

56F807

Technical Data Sheet

Electrical and timing specifications, pin descriptions,

and package descriptions (this document)

DSP56F807

56F807E

56F807

Errata

Details any chip issues that might be present

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

This is used to indicate a signal that is active when pulled low. For example, the RESET pin is

active when low.

“asserted”

“deasserted”

Examples:

A high true (active high) signal is high or a low true (active low) signal is low.

A high true (active high) signal is low or a low true (active low) signal is high.

Voltage¹

Signal/Symbol

Logic State

True

Signal State

Asserted

V_IL/V_OL

False

Deasserted

Asserted

V_IH/V_OH

V_IL/V_OL

True

False

Deasserted

1. Values for V_IL, V_OL, V_IH, and V_OHare defined by individual product specifications.

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

7

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F807 are organized into functional groups, as shown in Table 2-1

and as illustrated in Figure 2-1. In Table 2-2 through Table 2-19, each table row describes the signal or

signals present on a pin.

Table 2-1 Functional Group Pin Allocations

Number of

Pins

Detailed

Description

Functional Group

Power (V_DDor V_DDA

)

11

13

4

Table 2-2

Table 2-3

Table 2-4

Ground (V_SSor V_SSA

)

Supply Capacitors & V_PP

PLL and Clock

3

Table 2-5

Table 2-6

Address Bus¹

16

Data Bus

16

4

Table 2-7

Table 2-8

Table 2-9

Table 2-10

Table 2-11

Table 2-12

Bus Control

Interrupt and Program Control

Dedicated General Purpose Input/Output

Pulse Width Modulator (PWM) Ports

5

14

26

4

Serial Peripheral Interface (SPI) Port¹

Quadrature Decoder Ports²

8

4

Table 2-13

Table 2-15

Serial Communications Interface (SCI) Ports¹

CAN Port

2

20

6

Table 2-16

Table 2-17

Table 2-18

Table 2-19

Analog to Digital Converter (ADC) Ports

Quad Timer Module Ports

JTAG/On-Chip Emulation (OnCE)

1. Alternately, GPIO pins

6

2. Alternately, Quad Timer pins

56F807 Technical Data Technical Data, Rev. 15

8

Freescale Semiconductor

Introduction

V_DD

V_SS

8

Power Port

Ground Port

Power Port

Ground Port

GPIOB0–7

GPIOD0–5

Dedicated

GPIO

8

6

10*

3

V_DDA

V_SSA

3

PWMA0-5

ISA0-2

6

3

4

PWMA

Port

VCAPC

V_PP

Other

Supply

Ports

2

FAULTA0-3

PWMB0-5

ISB0-2

6

3

4

EXTAL

XTAL

PLL

and

Clock

1

PWMB

Port

56F807

FAULTB0-3

CLKO

SCLK (GPIOE4)

MOSI (GPIOE5)

MISO (GPIOE6)

SS (GPIOE7)

1

A0-A5

A6-7 (GPIOE2-E3)

A8-15 (GPIOA0-A7)

6

2

8

External

Address Bus or

GPIO

SPI Port

or GPIO

External

Data Bus

D0–D15

16

TXD0 (GPIOE0)

RXD0 (GPIOE1)

1

SCI0 Port

or GPIO

PS

DS

1

External

Bus Control

SCI1 Port

or GPI0

TXD1 (GPIOD6)

RXD1 (GPIOD7)

1

RD

WR

ADCA

Port

ANA0-7

VREF

8

2

8

PHASEA0 (TA0)

PHASEB0 (TA1)

INDEX0 (TA2)

HOME0 (TA3)

PHASEA1 (TB0)

PHASEB1 (TB1)

INDEX1 (TB2)

HOME1 (TB3)

TCK

1

Quadrature

Decoder or

Quad Timer A

ADCB

Port

ANB0-7

MSCAN_RX

MSCAN_TX

1

CAN

Quadrature

Decoder1 or

Quad Timer B

Quad

Timers

C & D

TC0-1

TD0-3

2

4

TMS

IRQA

1

TDI

IRQB

JTAG/OnCE™

Interrupt/

Program

Control

TDO

Port

RESET

RSTO

TRST

EXTBOOT

DE

*includes TCS pin which is reserved for factory use and is tied to VSS

1

Figure 2-1 56F807 Signals Identified by Functional Group

1. Alternate pin functionality is shown in parenthesis.

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

9

2.2 Power and Ground Signals

Table 2-2 Power Inputs

No. of Pins

Signal Name

V_DD

Signal Description

8

Power—These pins provide power to the internal structures of the chip, and should

all be attached to V_DD.

3

V_DDA

Analog Power—These pins is a dedicated power pin for the analog portion of the

chip and should be connected to a low noise 3.3V supply.

Table 2-3 Grounds

No. of Pins

Signal Name

V_SS

Signal Description

9

GND—These pins provide grounding for the internal structures of the chip and should

all be attached to V_SS.

3

1

V_SSA

TCS

Analog Ground—This pin supplies an analog ground.

TCS—This Schmitt pin is reserved for factory use and must be tied to V_SSfor normal

use. In block diagrams, this pin is considered an additional V_SS.

Table 2-4 Supply Capacitors and VPP

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

2

VCAPC

Supply

VCAPC—Connect each pin to a 2.2uF or greater bypass capacitor in

order to bypass the core logic voltage regulator (required for proper chip

operation). For more information, please refer to Section 5.2

2

VPP

Input

VPP—This pin should be left unconnected as an open circuit for normal

functionality.

56F807 Technical Data Technical Data, Rev. 15

10

Freescale Semiconductor

Clock and Phase Locked Loop Signals

2.3 Clock and Phase Locked Loop Signals

Table 2-5 PLL and Clock

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

1

EXTAL

Input

External Crystal Oscillator Input—This input should be connected to

an 8MHz external crystal or ceramic resonator. For more information,

please refer to Section 3.4.

1

XTAL

Input/

Output

Chip-driven

Crystal Oscillator Output—This output should be connected to an

8MHz external crystal or ceramic resonator. For more information, please

refer to Section 3.4.

This pin can also be connected to an external clock source. For more

information, please refer to Section 3.4.2.

1

CLKO

Output

Chip-driven

Clock Output—This pin outputs a buffered clock signal. By programming

the CLKOSEL[4:0] bits in the CLKO Select Register (CLKOSR), the user

can select between outputting a version of the signal applied to XTAL and

a version of the device’s master clock at the output of the PLL. The clock

frequency on this pin can also be disabled by programming the

CLKOSEL[4:0] bits in CLKOSR.

2.4 Address, Data, and Bus Control Signals

Table 2-6 Address Bus Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

6

A0–A5

Output

Tri-stated

Address Bus—A0–A5 specify the address for external Program or

Data memory accesses.

2

A6–A7

Output

Tri-stated

Address Bus—A6–A7 specify the address for external Program or

Data memory accesses.

GPIOE2-

GPIOE3

Input/O

utput

Input

Port E GPIO—These two General Purpose I/O (GPIO) pins can

individually be programmed as input or output pins.

After reset, the default state is Address Bus.

8

A8–A15

Output

Tri-stated

Input

Address Bus—A8–A15 specify the address for external Program or

Data memory accesses.

GPIOA0-

GPIOA7

Input/O

utput

Port A GPIO—These eight General Purpose I/O (GPIO) pins can be

individually programmed as input or output pins.

After reset, the default state is Address Bus.

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

11

Table 2-7 Data Bus Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Signal Description

Reset

16

D0–D15

Input/O

utput

Tri-stated

Data Bus— D0–D15 specify the data for external program or data

memory accesses. D0–D15 are tri-stated when the external bus is

inactive. Internal pullups may be active.

Table 2-8 Bus Control Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Signal Description

Reset

1

PS

DS

WR

Output

Tri-stated

Program Memory Select—PS is asserted low for external program

memory access.

Output

Tri-stated

Data Memory Select—DS is asserted low for external data memory

access.

Write Enable—WR is asserted during external memory write cycles.

When WR is asserted low, pins D0–D15 become outputs and the device

puts data on the bus. When WR is deasserted high, the external data is

latched inside the external device. When WR is asserted, it qualifies the

A0–A15, PS, and DS pins. WR can be connected directly to the WE pin of

a Static RAM.

1

RD

Output

Tri-stated

Read Enable—RD is asserted during external memory read cycles. When

RD is asserted low, pins D0–D15 become inputs and an external device is

enabled onto the device’s data bus. When RD is deasserted high, the

external data is latched inside the device. When RD is asserted, it qualifies

the A0–A15, PS, and DS pins. RD can be connected directly to the OE pin

of a Static RAM or ROM.

2.5 Interrupt and Program Control Signals

Table 2-9 Interrupt and Program Control Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

1

IRQA

Input

(Schmitt)

Input

External Interrupt Request A—The IRQA input is a synchronized

external interrupt request that indicates that an external device is

requesting service. It can be programmed to be level-sensitive or

negative-edge-triggered.

1

IRQB

Input

(Schmitt)

External Interrupt Request B—The IRQB input is an external

interrupt request that indicates that an external device is requesting

service. It can be programmed to be level-sensitive or

negative-edge-triggered.

56F807 Technical Data Technical Data, Rev. 15

12

Freescale Semiconductor

GPIO Signals

Table 2-9 Interrupt and Program Control Signals (Continued)

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

1

RSTO

Output

Reset Output—This output reflects the internal reset state of the

chip.

1

RESET

Input

(Schmitt)

Input

Reset—This input is a direct hardware reset on the processor. When

RESET is asserted low, the device is initialized and placed in the

Reset state. A Schmitt trigger input is used for noise immunity. When

the RESET pin is deasserted, the initial chip operating mode is

latched from the EXTBOOT pin. The internal reset signal will be

deasserted synchronous with the internal clocks, after a fixed number

of internal clocks.

To ensure complete hardware reset, RESET and TRST should be

asserted together. The only exception occurs in a debugging

environment when a hardware device reset is required and it is

necessary not to reset the OnCE/JTAG module. In this case, assert

RESET, but do not assert TRST.

1

EXTBOOT

Input

External Boot—This input is tied to V_DDto force device to boot from

(Schmitt)

off-chip memory. Otherwise, it is tied to VSS.

2.6 GPIO Signals

Table 2-10 Dedicated General Purpose Input/Output (GPIO) Signals

No.of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

8

GPIOB0-

GPIOB7

Input

or

Output

Input

Port B GPIO—These eight pins are dedicated General Purpose I/O

(GPIO) pins that can individually be programmed as input or output

pins.

After reset, the default state is GPIO input.

6

GPIOD0-

GPIOD5

Input

or

Input

Port D GPIO—These six pins are dedicated GPIO pins that can

individually be programmed as an input or output pins.

Output

After reset, the default state is GPIO input.

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

13

2.7 Pulse Width Modulator (PWM) Signals

Table 2-11 Pulse Width Modulator (PWMA and PWMB) Signals

No.of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

6

3

PWMA0-5

ISA0-2

Output

Tri- stated

Input

PWMA0-5— Six PWMA output pins.

Input

(Schmitt)

ISA0-2— These three input current status pins are used for

top/bottom pulse width correction in complementary channel

operation for PWMA.

4

FAULTA0-3

Input

(Schmitt)

Input

FAULTA0-3— These Fault input pins are used for disabling

selected PWMA outputs in cases where fault conditions originate

off-chip.

6

3

PWMB0-5

ISB0-2

Output

Tri- stated

Input

PWMB0-5— Six PWMB output pins.

Input

(Schmitt)

ISB0-2— These three input current status pins are used for

top/bottom pulse width correction in complementary channel

operation for PWMB.

4

FAULTB0-3

Input

(Schmitt)

Input

FAULTB0-3— These four Fault input pins are used for disabling

selected PWMB outputs in cases where fault conditions originate

off-chip.

56F807 Technical Data Technical Data, Rev. 15

14

Freescale Semiconductor

Serial Peripheral Interface (SPI) Signals

2.8 Serial Peripheral Interface (SPI) Signals

Table 2-12 Serial Peripheral Interface (SPI) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

1

MISO

Input/

Output

Input

SPI Master In/Slave Out (MISO)—This serial data pin is an input to a

master device and an output from a slave device. The MISO line of a

slave device is placed in the high-impedance state if the slave device is

not selected.

GPIOE6 Input/Outp

Input

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can

individually be programmed as input or output pin.

ut

After reset, the default state is MISO.

1

MOSI

Input/

SPI Master Out/Slave In (MOSI)—This serial data pin is an output from

a master device and an input to a slave device. The master device

places data on the MOSI line a half-cycle before the clock edge that the

slave device uses to latch the data.

Output

GPIOE5 Input/Outp

Input

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can

ut

individually be programmed as input or output pin.

After reset, the default state is MOSI.

1

SCLK

Input/Outp

ut

Input

SPI Serial Clock—In master mode, this pin serves as an output,

clocking slaved listeners. In slave mode, this pin serves as the data

clock input.

GPIOE4 Input/Outp

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can

ut

individually be programmed as input or output pin.

After reset, the default state is SCLK.

1

SS

Input

SPI Slave Select—In master mode, this pin is used to arbitrate multiple

masters. In slave mode, this pin is used to select the slave.

GPIOE7 Input/Outp

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can

ut

individually be programmed as input or output pin.

After reset, the default state is SS.

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

15

2.9 Quadrature Decoder Signals

Table 2-13 Quadrature Decoder (Quad Dec0 and Quad Dec1) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

1

PHASEA0

Input

Phase A—Quadrature Decoder #0 PHASEA input

TA0

Input/Output

Input

TA0—Timer A Channel 0

PHASEB0

Phase B—Quadrature Decoder #0 PHASEB input

TA1

Input/Output

Input

TA1—Timer A Channel 1

INDEX0

Index—Quadrature Decoder #0 INDEX input

TA2

Input/Output

Input

TA2—Timer A Channel 2

HOME0

Home—Quadrature Decoder #0 HOME input

TA3

Input/Output

Input

TA3—Timer A Channel 3

PHASEA1

Phase A—Quadrature Decoder #1 PHASEA input

TB0

Input/Output

Input

TB0—Timer B Channel 0

PHASEB1

Phase B—Quadrature Decoder #1 PHASEB input

TB1

Input/Output

Input

TB1—Timer B Channel 1

INDEX1

Index—Quadrature Decoder #1 INDEX input

TB2

Input/Output

Input

TB2—Timer B Channel 2

HOME1

Home—Quadrature Decoder #1 HOME input

TB3

Input/Output

Input

TB3—Timer B Channel 3

56F807 Technical Data Technical Data, Rev. 15

16

Freescale Semiconductor

Serial Communications Interface (SCI) Signals

2.10 Serial Communications Interface (SCI) Signals

Table 2-14 Serial Peripheral Interface (SPI) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

1

MISO

Input/

Output

Input

SPI Master In/Slave Out (MISO)—This serial data pin is an input to a

master device and an output from a slave device. The MISO line of a

slave device is placed in the high-impedance state if the slave device is

not selected.

GPIOE6 Input/Outp

Input

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can

individually be programmed as input or output pin.

ut

After reset, the default state is MISO.

1

MOSI

Input/

SPI Master Out/Slave In (MOSI)—This serial data pin is an output from

a master device and an input to a slave device. The master device

places data on the MOSI line a half-cycle before the clock edge that the

slave device uses to latch the data.

Output

GPIOE5 Input/Outp

Input

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can

ut

individually be programmed as input or output pin.

After reset, the default state is MOSI.

1

SCLK

Input/Outp

ut

Input

SPI Serial Clock—In master mode, this pin serves as an output,

clocking slaved listeners. In slave mode, this pin serves as the data

clock input.

GPIOE4 Input/Outp

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can

ut

individually be programmed as input or output pin.

After reset, the default state is SCLK.

1

SS

Input

SPI Slave Select—In master mode, this pin is used to arbitrate multiple

masters. In slave mode, this pin is used to select the slave.

GPIOE7 Input/Outp

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can

ut

individually be programmed as input or output pin.

After reset, the default state is SS.

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

17

Table 2-15 Serial Communications Interface (SCI0 and SCI1) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

1

TXD0

Output

Input

Transmit Data (TXD0)—transmit data output

GPIOE0

Input/Outp

ut

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that

can individually be programmed as input or output pin.

After reset, the default state is SCI output.

RXD0

Input

Receive Data (RXD0)— receive data input

GPIOE1

Input/Outp

ut

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that

can individually be programmed as input or output pin.

After reset, the default state is SCI input.

TXD1

Output

Input

Transmit Data (TXD1)—transmit data output

GPIOD6

Input/Outp

ut

Port D GPIO—This pin is a General Purpose I/O (GPIO) pin that

can individually be programmed as input or output pin.

After reset, the default state is SCI output.

RXD1

Input

Receive Data (RXD1)— receive data input

GPIOD7

Input/Outp

ut

Port D GPIO—This pin is a General Purpose I/O (GPIO) pin that

can individually be programmed as input or output pin.

After reset, the default state is SCI input.

2.11 CAN Signals

Table 2-16 CAN Module Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Signal Description

Reset

1

MSCAN_ RX

Input

MSCAN Receive Data—MSCAN input. This pin has an internal

(Schmitt)

pull-up resistor.

1

MSCAN_ TX

Output

MSCAN Transmit Data—MSCAN output. CAN output is

open-drain output and pull-up resistor is needed.

56F807 Technical Data Technical Data, Rev. 15

18

Freescale Semiconductor

Analog-to-Digital Converter (ADC) Signals

2.12 Analog-to-Digital Converter (ADC) Signals

Table 2-17 Analog to Digital Converter Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

4

2

ANA0-3

ANA4-7

VREF

Input

ANA0-3—Analog inputs to ADCA channel 1

ANA4-7—Analog inputs to ADCA channel 2

VREF—Analog reference voltage for ADC. Must be set to

V_DDA-0.3V for optimal performance.

4

ANB0-3

ANB4-7

Input

ANB0-3—Analog inputs to ADCB, channel 1

ANB4-7—Analog inputs to ADCB, channel 2

2.13 Quad Timer Module Signals

Table 2-18 Quad Timer Module Signals

No. of

Pins

Signal

Name

State During

Signal Type

Signal Description

Reset

2

4

TC0-1

TD0-3

Input/Output

Input

TC0-1—Timer C Channels 0 and 1

TD0-3—Timer D Channels 0, 1, 2, and 3

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

19

2.14 JTAG/OnCE

Table 2-19 JTAG/On-Chip Emulation (OnCE) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

1

TCK

Input

(Schmitt)

Input, pulled Test Clock Input—This input pin provides a gated clock to synchronize

low internally the test logic and shift serial data to the JTAG/OnCE port. The pin is

connected internally to a pull-down resistor.

1

TMS

Input

(Schmitt)

Input, pulled Test Mode Select Input—This input pin is used to sequence the JTAG

high internally TAP controller’s state machine. It is sampled on the rising edge of TCK

and has an on-chip pull-up resistor.

Note: Always tie the TMS pin to V_DDthrough a 2.2K resistor.

1

TDI

TDO

TRST

Input

(Schmitt)

Input, pulled Test Data Input—This input pin provides a serial input data stream to

high internally the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an

on-chip pull-up resistor.

Output

Tri-stated

Test Data Output—This tri-statable output pin provides a serial output

data stream from the JTAG/OnCE port. It is driven in the Shift-IR and

Shift-DR controller states, and changes on the falling edge of TCK.

Input

(Schmitt)

Input, pulled Test Reset—As an input, a low signal on this pin provides a reset signal

high internally to the JTAG TAP controller. To ensure complete hardware reset, TRST

should be asserted at power-up and whenever RESET is asserted. The

only exception occurs in a debugging environment when a hardware

device reset is required and it is necessary not to reset the OnCE/JTAG

module. In this case, assert RESET, but do not assert TRST.

Note: For normal operation, connect TRST directly to V_SS. If the design is to

be used in a debugging environment, TRST may be tied to V_SSthrough a 1K

resistor.

1

DE

Output

Debug Event—DE provides a low pulse on recognized debug events.

Part 3 Specifications

3.1 General Characteristics

The 56F807 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term

“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to

withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices

designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible

I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during

normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings

of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the

maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent

56F807 Technical Data Technical Data, Rev. 15

20

Freescale Semiconductor

General Characteristics

damage to the device.

The 56F807 DC/AC electrical specifications are preliminary and are from design simulations. These

specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized

specifications will be published after complete characterization and device qualifications have been

completed.

CAUTION

This device contains protective circuitry to guard against

damage due to high static voltage or electrical fields. However,

normal precautions are advised to avoid application of any

voltages higher than maximum rated voltages to this

high-impedance circuit. Reliability of operation is enhanced if

unused inputs are tied to an appropriate voltage level.

Table 3-1 Absolute Maximum Ratings

Characteristic

Symbol

V_DD

V_IN

Min

V_SS– 0.3

- 0.3

Max

V_SS+ 4.0

V_SS+ 5.5V

0.3

Unit

V

Supply voltage

All other input voltages, excluding Analog inputs

Voltage difference V_DDto V_DDA

V

ΔV_DD

ΔV_SS

V_IN

V

Voltage difference V_SSto V_SSA

- 0.3

0.3

V

Analog inputs, ANA0-7 and VREF

Analog inputs EXTAL and XTAL

V_SSA– 0.3

—

V_DDA+ 0.3

V_SSA+ 3.0

10

V

V_IN

V

Current drain per pin excluding V_DD, V_SS, PWM

outputs, TCS, VPP, V_DDA, V_SSA

I

mA

Table 3-2 Recommended Operating Conditions

Characteristic

Supply voltage, digital

Symbol

V_DD

Min

3.0

Typ

3.3

-

Max

3.6

0.1

Unit

V

Supply Voltage, analog

V_DDA

ΔV_DD

3.0

Voltage difference V_DDto V_DDA

-0.1

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

21

Table 3-2 Recommended Operating Conditions

Characteristic

Symbol

ΔV_SS

VREF

T_A

Min

-0.1

2.7

Typ

Max

0.1

Unit

V

Voltage difference V_SSto V_SSA

-

ADC reference voltage

–

V_DDA

85

V

Ambient operating temperature

–40

°C

6

Table 3-3 Thermal Characteristics

Value

Characteristic

Symbol

Unit

Notes

Comments

160-pin

LQFP

160

MBGA

Junction to ambient

Natural convection

R_θJA

38.5

63.4

°C/W

2

Junction to ambient (@1m/sec)

R_θJMA

35.4

33

60.3

49.9

°C/W

2

Junction to ambient

Natural convection

Four layer

board (2s2p)

R_θJMA

(2s2p)

1,2

Junction to ambient (@1m/sec)

Four layer

R_θJMA

31.5

46.8

°C/W

1,2

board (2s2p)

Junction to case

R_θJC

Ψ_JT

8.6

0.8

8.1

0.6

°C/W

W

3

Junction to center of case

I/O pin power dissipation

Power dissipation

4, 5

P _I/O

P _D

User Determined

P _D= (I_DDx V_DD+ P _I/O

(TJ - TA) /RθJA

)

W

Junction to center of case

P_DMAX

W

7

Notes:

1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.

Determined on 2s2p thermal test board.

2. Junction to ambient thermal resistance, Theta-JA (R_θJA) was simulated to be equivalent to the JEDEC

specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on

a thermal test board with two internal planes (2s2p where “s” is the number of signal layers and “p” is the

number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with

the non-single layer boards is Theta-JMA.

3. Junction to case thermal resistance, Theta-JC (R_θJC), was simulated to be equivalent to the measured values

using the cold plate technique with the cold plate temperature used as the “case” temperature. The basic cold

plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal

metric to use to calculate thermal performance when the package is being used with a heat sink.

56F807 Technical Data Technical Data, Rev. 15

22

Freescale Semiconductor

DC Electrical Characteristics

4. Thermal Characterization Parameter, Psi-JT (Ψ_JT), is the “resistance” from junction to reference point

thermocouple on top center of case as defined in JESD51-2. Ψ_JTis a useful value to use to estimate junction

temperature in steady state customer environments.

5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and

board thermal resistance.

6. See Section 5.1 from more details on thermal design considerations.

7. TJ = Junction Temperature

TA = Ambient Temperature

3.2 DC Electrical Characteristics

Table 3-4 DC Electrical Characteristics

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6 V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Characteristic

Input high voltage (XTAL/EXTAL)

Symbol

V_IHC

V_ILC

V_IHS

V_ILS

V_IH

Min

2.25

0

Typ

—

30

—

Max

2.75

0.5

5.5

0.8

5.5

0.8

1

Unit

V

Input low voltage (XTAL/EXTAL)

V

Input high voltage (Schmitt trigger inputs)¹

2.2

-0.3

2.0

-0.3

-1

V

Input low voltage (Schmitt trigger inputs)¹

Input high voltage (all other digital inputs)

V

Input low voltage (all other digital inputs)

V_IL

V

Input current high (pullup/pulldown resistors disabled, V_IN=V_DD

)

I_IH

μA

KΩ

μA

Input current low (pullup/pulldown resistors disabled, V_IN=V_SS

Input current high (with pullup resistor, V_IN=V_DD

Input current low (with pullup resistor, V_IN=V_SS

Input current high (with pulldown resistor, V_IN=V_DD

)

I_IL

-1

1

)

I_IHPU

I_ILPU

I_IHPD

I_ILPD

-1

1

)

-210

20

-50

180

1

)

Input current low (with pulldown resistor, V_IN=V_SS

Nominal pullup or pulldown resistor value

Output tri-state current low

)

-1

R

_PU, R_PD

I_OZL

-10

-15

10

15

Output tri-state current high

I_OZH

2

I_IHA

Input current high (analog inputs, V_IN=V_DDA

)

3

I_ILA

-15

—

15

—

μA

Input current low (analog inputs, V_IN=V_SSA

)

Output High Voltage (at IOH)

V_OH

V_DD– 0.7

V

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

23

Table 3-4 DC Electrical Characteristics (Continued)

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6 V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Characteristic

Output Low Voltage (at IOL)

Symbol

V_OL

Min

—

4

Typ

—

8

Max

0.4

—

Unit

V

Output source current

I_OH

mA

pF

I_OL

4

—

PWM pin output source current³

I_OHP

I_OLP

C_IN

10

16

—

PWM pin output sink current⁴

Input capacitance

—

Output capacitance

C_OUT

12

—

pF

5

V_DDsupply current

I_DDT

Run ⁶

—

195

170

220

200

mA

Wait⁷

Stop

—

115

2.7

145

3.0

mA

V

Low Voltage Interrupt, external power supply⁸

Low Voltage Interrupt, internal power supply⁹

Power on Reset¹⁰

V_EIO

V_EIC

2.4

2.0

—

2.2

1.7

2.4

2.0

V

V_POR

1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, ISA0-2, FAULTA0-3, ISB0-2, FAULTB0-3, TCK, TRST, TMS,

TDI, and MSCAN_RX

2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.

3. PWM pin output source current measured with 50% duty cycle.

4. PWM pin output sink current measured with 50% duty cycle.

5. I_DDT= I_DD+ I_DDA(Total supply current for V_DD+ V_DDA

)

6. Run (operating) I_DDmeasured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs;

measured with all modules enabled.

7. Wait I_DDmeasured using external square wave clock source (f_osc= 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less

than 50pF on all outputs. C_L= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait I_DD; measured

with PLL enabled.

8. This low voltage interrupt monitors the V_DDAexternal power supply. V_DDAis generally connected to the same potential as V_DDvia

separate traces. If V_DDAdrops below V_EIO, an interrupt is generated. Functionality of the device is guaranteed under transient condi-

tions when V_DDA>V_EIO(between the minimum specified V_DDand the point when the V_EIOinterrupt is generated).

9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator

drops below V_EIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless

the external power supply drops below the minimum specified value (3.0V).

10. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up,

this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate is. The internally

regulated voltage is typically 100mV less than V_DDduring ramp-up until 2.5V is reached, at which time it self-regulates.

56F807 Technical Data Technical Data, Rev. 15

24

Freescale Semiconductor

AC Electrical Characteristics

250

200

150

100

50

IDD Analog

IDD Total

IDD Digital

0

10

20

60

70

80

50

30

40

Freq. (MHz)

Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-14)

3.3 AC Electrical Characteristics

Timing waveforms in Section 3.3 are tested using the V_ILand V_IHlevels specified in the DC Characteristics

table. In Figure 3-2 the levels of V_IHand V_ILfor an input signal are shown.

Low

V_IL

High

V_IH

90%

50%

10%

Input Signal

Midpoint1

Fall Time

Note: The midpoint is V_IL+ (V_IH– V_IL)/2.

Rise Time

Figure 3-2 Input Signal Measurement References

Figure 3-3 shows the definitions of the following signal states:

•

Active state, when a bus or signal is driven, and enters a low impedance state

Tri-stated, when a bus or signal is placed in a high impedance state

Data Valid state, when a signal level has reached V_OLor V_OH

•

Data Invalid state, when a signal level is in transition between V_OLand V_OH

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

25

Data2 Valid

Data2

Data1 Valid

Data1

Data3 Valid

Data3

Data

Tri-stated

Data Invalid State

Data Active

Figure 3-3 Signal States

Table 3-5 Flash Memory Truth Table

XE¹

YE²

SE³

OE⁴

PROG⁵

ERASE⁶

MAS1⁷

NVSTR⁸

Mode

Standby

Read

L

H

L

H

L

H

L

H

L

H

L

H

Word Program

Page Erase

Mass Erase

L

H

L

1. X address enable, all rows are disabled when XE=0

2. Y address enable, YMUX is disabled when YE=0

3. Sense amplifier enable

4. Output enable, tri-state Flash data out bus when OE=0

5. Defines program cycle

6. Defines erase cycle

7. Defines mass erase cycle, erase whole block

8. Defines non-volatile store cycle

Table 3-6 IFREN Truth Table

Mode

IFREN=1

IFREN=0

Read

Read information block

Program information block

Erase information block

Erase both block

Read main memory block

Program main memory block

Erase main memory block

Word program

Page erase

Mass erase

56F807 Technical Data Technical Data, Rev. 15

26

Freescale Semiconductor

AC Electrical Characteristics

Table 3-7 Flash Timing Parameters

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6V, T_A= –40° to +85°C, C_L≤ 50pF

Characteristic

Program time

Symbol

Min

20

Typ

Max

Unit

us

Figure

–

Figure 3-4

Figure 3-5

Figure 3-6

Tprog*

Terase*

Tme*

Erase time

20

–

ms

Mass erase time

100

10,000

10

ms

Endurance¹

E_CYC

20,000

30

cycles

years

Data Retention¹

D_RET

The following parameters should only be used in the Manual Word Programming Mode

PROG/ERASE to NVSTR set

up time

–

5

–

us

Figure 3-4,

Figure 3-5,

Figure 3-6

Tnvs*

NVSTR hold time

Figure 3-4,

Figure 3-5

Tnvh*

NVSTR hold time (mass erase)

NVSTR to program set up time

Recovery time

–

100

10

1

–

us

Figure 3-6

Figure 3-4

Tnvh1*

Tpgs*

Trcv*

Figure 3-4,

Figure 3-5,

Figure 3-6

Cumulative program

HV period²

–

3

–

ms

Figure 3-4

Thv

Program hold time³

–

Figure 3-4

Tpgh

Tads

Tadh

Address/data set up time³

Address/data hold time³

1. One cycle is equal to an erase program and read.

2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be

programmed twice before next erase.

3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.

*The Flash interface unit provides registers for the control of these parameters.

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

27

IFREN

XADR

XE

Tadh

YADR

YE

DIN

Tads

PROG

NVSTR

Tnvs

Tprog

Tpgh

Tpgs

Tnvh

Trcv

Thv

Figure 3-4 Flash Program Cycle

IFREN

XADR

XE

YE=SE=OE=MAS1=0

ERASE

NVSTR

Tnvs

Tnvh

Trcv

Terase

Figure 3-5 Flash Erase Cycle

56F807 Technical Data Technical Data, Rev. 15

28

Freescale Semiconductor

External Clock Operation

IFREN

XADR

XE

MAS1

YE=SE=OE=0

ERASE

NVSTR

Tnvs

Tnvh1

Trcv

Tme

Figure 3-6 Flash Mass Erase Cycle

3.4 External Clock Operation

The 56F807 system clock can be derived from an external crystal or an external system clock signal. To

generate a reference frequency using the internal oscillator, a reference crystal must be connected between

the EXTAL and XTAL pins.

3.4.1

Crystal Oscillator

The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the

frequency range specified for the external crystal in Table 3-9. In Figure 3-7 a recommended crystal

oscillator circuit is shown. Follow the crystal supplier’s recommendations when selecting a crystal, since

crystal parameters determine the component values required to provide maximum stability and reliable

start-up. The crystal and associated components should be mounted as close as possible to the EXTAL

and XTAL pins to minimize output distortion and start-up stabilization time. The internal 56F80x

oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-8 no

external load capacitors should be used.

The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a

capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and

process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

29

as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as

determined by the following equation:

CL1 * CL2

CL1 + CL2

12 * 12

12 + 12

CL =

+ Cs =

+ 3 = 6 + 3 = 9pF

This is the value load capacitance that should be used when selecting a crystal and determining the actual

frequency of operation of the crystal oscillator circuit.

Recommended External Crystal

Parameters:

EXTAL XTAL

R_z

f_c

R_z= 1 to 3 MΩ

f_c= 8MHz (optimized for 8MHz)

Figure 3-7 Connecting to a Crystal Oscillator

3.4.2

Ceramic Resonator

It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system

design can tolerate the reduced signal integrity. In Figure 3-8, a typical ceramic resonator circuit is

shown. Refer to supplier’s recommendations when selecting a ceramic resonator and associated

components. The resonator and components should be mounted as close as possible to the EXTAL and

XTAL pins. The internal 56F80x oscillator circuitry is designed to have no external load capacitors

present. As shown in Figure 3-7 no external load capacitors should be used.

Recommended Ceramic Resonator

EXTAL XTAL

Parameters:

R_z= 1 to 3 MΩ

R_z

f_c= 8MHz (optimized for 8MHz)

f_c

Figure 3-8 Connecting a Ceramic Resonator

Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators

(which contain an internal bypass capacitor to ground).

56F807 Technical Data Technical Data, Rev. 15

30

Freescale Semiconductor

External Clock Operation

3.4.3

External Clock Source

The recommended method of connecting an external clock is given in Figure 3-9. The external clock

source is connected to XTAL and the EXTAL pin is grounded.

56F807

XTAL

EXTAL

V

External

Clock

SS

Figure 3-9 Connecting an External Clock Signal

5

Table 3-8 External Clock Operation Timing Requirements

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6 V, T_A= –40° to +85°C

Characteristic

Symbol

f_osc

Min

0

Typ

—

Max

80

Unit

MHz

ns

Frequency of operation (external clock driver)¹

Clock Pulse Width², ³

t_PW

6.25

—

1. See Figure 3-9 for details on using the recommended connection of an external clock driver.

2. The high or low pulse width must be no smaller than 6.25ns or the chip will not function.

3. Parameters listed are guaranteed by design.

V_IH

External

Clock

90%

50%

10%

90%

50%

10%

V_IL

t_PW

Note: The midpoint is V_IL+ (V_IH– V_IL)/2.

Figure 3-10 External Clock Timing

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

31

3.4.4

Phase Locked Loop Timing

Table 3-9 PLL Timing

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6 V, T_A= –40° to +85°C

Characteristic

Symbol

f_osc

Min

4

Typ

8

Max

10

Unit

MHz

ms

External reference crystal frequency for the PLL¹

PLL output frequency²

f_out/2

t_plls

40

—

110

10

PLL stabilization time³0^oto +85^oC

PLL stabilization time³-40^oto 0^oC

1

t_plls

100

200

ms

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work

correctly. The PLL is optimized for 8MHz input crystal.2.

2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f_out/2, please refer to the OCCS chapter in the

User Manual. ZCLK = f_op

3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.

56F807 Technical Data Technical Data, Rev. 15

32

Freescale Semiconductor

External Bus Asynchronous Timing

3.5 External Bus Asynchronous Timing

1,2

Table 3-10 External Bus Asynchronous Timing

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6 V, T_A= –40° to +85°C, C_L≤ 50pF, f_op= 80MHz

Characteristic

Symbol

Unit

Min

Max

Address Valid to WR Asserted

t_AWR

t_WR

6.5

—

ns

WR Width Asserted

Wait states = 0

Wait states > 0

7.5

(T*WS)+7.5

—

ns

WR Asserted to D0–D15 Out Valid

t_WRD

t_DOH

t_DOS

—

T + 4.2

—

ns

Data Out Hold Time from WR Deasserted

4.8

Data Out Set Up Time to WR Deasserted

Wait states = 0

Wait states > 0

2.2

(T*WS)+6.4

—

ns

RD Deasserted to Address Not Valid

t_RDA

0

—

ns

Address Valid to RD Deasserted

Wait states = 0

Wait states > 0

t_ARDD

18.7

(T*WS) + 18.7

ns

Input Data Hold to RD Deasserted

t_DRD

t_RD

0

—

ns

RD Assertion Width

Wait states = 0

Wait states > 0

19

—

ns

(T*WS)+19

Address Valid to Input Data Valid

Wait states = 0

Wait states > 0

t_AD

—

1

ns

(T*WS)+1

Address Valid to RD Asserted

t_ARDA

t_RDD

-4.4

—

ns

RD Asserted to Input Data Valid

Wait states = 0

Wait states > 0

—

2.4

ns

(T*WS) + 2.4

WR Deasserted to RD Asserted

RD Deasserted to RD Asserted

WR Deasserted to WR Asserted

RD Deasserted to WR Asserted

t_WRRD

t_RDRD

t_WRWR

t_RDWR

6.8

0

—

ns

14.1

12.8

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

33

1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and

T = Clock Period. For 80MHz operation, T = 12.5ns.

2. Parameters listed are guaranteed by design.

To calculate the required access time for an external memory for any frequency < 80MHz, use this formula:

Top = Clock period @ desired operating frequency

WS = Number of wait states

Memory Access Time = (Top*WS) + (Top- 11.5)

A0–A15,

PS, DS

t_ARDD

(See Note)

t_RDA

t_ARDA

t_RDRD

t_RD

t_AWR

t_WRWR

RD

t_WRRD

t_WR

t_RDWR

WR

t_RDD

t_AD

t_DOH

t_WRD

t_DRD

t_DOS

Data In

Data Out

D0–D15

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

Figure 3-11 External Bus Asynchronous Timing

56F807 Technical Data Technical Data, Rev. 15

34

Freescale Semiconductor

Reset, Stop, Wait, Mode Select, and Interrupt Timing

3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing

1,5

Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6 V, T_A= –40° to +85°C, C_L≤ 50pF

Characteristic

Symbol

Min

Max

Unit

See Figure

3-12

RESET Assertion to Address, Data and Control Signals

High Impedance

t_RAZ

—

21

ns

Minimum RESET Assertion Duration²

OMR Bit 6 = 0

OMR Bit 6 = 1

t_RA

3-12

275,000T

128T

—

ns

RESET Deassertion to First External Address Output

Edge-sensitive Interrupt Request Width

t_RDA

t_IRW

t_IDM

33T

1.5T

15T

34T

—

ns

3-12

3-13

3-14

IRQA, IRQB Assertion to External Data Memory Access

Out Valid, caused by first instruction execution in the

interrupt service routine

—

IRQA, IRQB Assertion to General Purpose Output Valid,

caused by first instruction execution in the interrupt

service routine

t_IG

16T

—

ns

3-14

3-15

IRQA Low to First Valid Interrupt Vector Address Out

recovery from Wait State³

t_IRI

13T

2T

—

ns

IRQA Width Assertion to Recover from Stop State⁴

t_IW

t_IF

3-16

Delay from IRQA Assertion to Fetch of first instruction

(exiting Stop)

OMR Bit 6 = 0

OMR Bit 6 = 1

—

275,000T

12T

ns

Duration for Level Sensitive IRQA Assertion to Cause

the Fetch of First IRQA Interrupt Instruction (exiting Stop)

OMR Bit 6 = 0

t_IRQ

3-17

—

275,000T

12T

ns

OMR Bit 6 = 1

Delay from Level Sensitive IRQA Assertion to First

Interrupt Vector Address Out Valid (exiting Stop)

OMR Bit 6 = 0

t_II

—

275,000T

12T

ns

OMR Bit 6 = 1

1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.

2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:

• After power-on reset

• When recovering from Stop state

3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is

not the minimum required so that the IRQA interrupt is accepted.

4. The interrupt instruction fetch is visible on the pins only in Mode 3.

5. Parameters listed are guaranteed by design.

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

35

RESET

t_RA

t_RAZ

t_RDA

First Fetch

A0–A15,

D0–D15

PS, DS,

RD, WR

First Fetch

Figure 3-12 Asynchronous Reset Timing

IRQA,

IRQB

t_IRW

Figure 3-13 External Interrupt Timing (Negative-Edge-Sensitive)

A0–A15,

PS, DS,

RD, WR

First Interrupt Instruction Execution

t_IDM

IRQA,

IRQB

a) First Interrupt Instruction Execution

General

Purpose

I/O Pin

t_IG

IRQA,

IRQB

b) General Purpose I/O

Figure 3-14 External Level-Sensitive Interrupt Timing

56F807 Technical Data Technical Data, Rev. 15

36

Freescale Semiconductor

Reset, Stop, Wait, Mode Select, and Interrupt Timing

IRQA,

IRQB

t_IRI

A0–A15,

PS, DS,

RD, WR

First Interrupt Vector

Instruction Fetch

Figure 3-15 Interrupt from Wait State Timing

t_IW

IRQA

t_IF

A0–A15,

PS, DS,

RD, WR

First Instruction Fetch

Not IRQA Interrupt Vector

Figure 3-16 Recovery from Stop State Using Asynchronous Interrupt Timing

t_IRQ

IRQA

t_II

A0–A15

PS, DS,

RD, WR

First IRQA Interrupt

Instruction Fetch

Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service

RSTO

t_RSTO

Figure 3-18 Reset Output Timing

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

37

3.7 Serial Peripheral Interface (SPI) Timing

1

Table 3-12 SPI Timing

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6 V, T_A= –40° to +85°C, C_L≤ 50pF, f_OP= 80MHz

Characteristic

Symbol

Min

Max

Unit

See Figure

Cycle time

Master

Slave

t_C

3-19-3-22

50

25

—

ns

Enable lead time

Master

Slave

t_ELD

t_ELG

t_CH

t_CL

3-22

—

25

—

ns

Enable lag time

Master

Slave

—

100

—

ns

Clock (SCK) high time

Master

Slave

3-19, 3-20, 3-21,

17.6

12.5

—

ns

3-22

Clock (SCK) low time

Master

Slave

3-22

24.1

25

—

ns

Data set-up time required for inputs

Master

Slave

t_DS

t_DH

t_A

3-19, 3-20, 3-21,

20

0

—

ns

3-22

Data hold time required for inputs

Master

Slave

3-19, 3-20, 3-21,

0

2

—

ns

3-22

Access time (time to data active from

high-impedance state)

Slave

3-22

4.8

3.7

15

ns

Disable time (hold time to high-impedance state)

Slave

t_D

15.2

Data Valid for outputs

Master

Slave (after enable edge)

t_DV

3-19, 3-20, 3-21,

—

4.5

20.4

ns

3-22

Data invalid

Master

Slave

t_DI

t_R

t_F

3-19, 3-20, 3-21,

0

—

ns

3-22

Rise time

Master

Slave

3-19, 3-20, 3-21,

—

11.5

10.0

ns

3-22

Fall time

Master

Slave

3-19, 3-20, 3-21,

—

9.7

9.0

ns

3-22

1. Parameters listed are guaranteed by design.

56F807 Technical Data Technical Data, Rev. 15

38

Freescale Semiconductor

Serial Peripheral Interface (SPI) Timing

SS

(Input)

SS is held High on master

t_C

t_R

t_F

t_CL

SCLK (CPOL = 0)

(Output)

t_CH

t_F

t_R

t_CL

SCLK (CPOL = 1)

(Output)

t_DH

t_CH

t_DS

MISO

(Input)

MSB in

t_DI

Bits 14–1

LSB in

t_DI(ref)

t_DV

MOSI

(Output)

Master MSB out

t_F

Bits 14–1

Master LSB out

t_R

Figure 3-19 SPI Master Timing (CPHA = 0)

SS

(Input)

SS is held High on master

t_C

t_F

t_R

t_CL

SCLK (CPOL = 0)

(Output)

t_CH

t_F

t_CL

SCLK (CPOL = 1)

(Output)

t_CH

t_DS

t_R

t_DH

MISO

MSB in

t_DI

Bits 14–1

LSB in

t_DI(ref)

(Input)

t_DV(ref)

t_DV

Bits 14– 1

MOSI

(Output)

Master MSB out

t_F

Master LSB out

t_R

Figure 3-20 SPI Master Timing (CPHA = 1)

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

39

SS

(Input)

t_C

t_F

t_R

t_ELG

t_CL

SCLK (CPOL = 0)

(Input)

t_CH

t_ELD

t_CL

SCLK (CPOL = 1)

(Input)

t_CH

t_A

t_F

t_D

t_R

MISO

(Output)

Slave MSB out

Bits 14–1

t_DV

Slave LSB out

t_DI

t_DS

t_DI

t_DH

MOSI

(Input)

MSB in

Bits 14–1

LSB in

Figure 3-21 SPI Slave Timing (CPHA = 0)

SS

(Input)

t_F

t_C

t_R

t_CL

SCLK (CPOL = 0)

(Input)

t_CH

t_ELG

t_ELD

t_CL

SCLK (CPOL = 1)

(Input)

t_DV

t_CH

t_R

t_A

t_D

Slave LSB out

t_DI

LSB in

t_F

MISO

(Output)

Slave MSB out

Bits 14–1

t_DV

t_DS

t_DH

MOSI

(Input)

MSB in

Bits 14–1

Figure 3-22 SPI Slave Timing (CPHA = 1)

56F807 Technical Data Technical Data, Rev. 15

40

Freescale Semiconductor

Quad Timer Timing

3.8 Quad Timer Timing

1, 2

Table 3-13 Timer Timing

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6 V, T_A= –40° to +85°C, C_L≤ 50pF, f_OP= 80MHz

Characteristic

Timer input period

Symbol

P_IN

Min

4T + 6

2T + 3

2T

Max

—

Unit

ns

Timer input high/low period

Timer output period

P_INHL

P_OUT

—

ns

—

ns

Timer output high/low period

P_OUTHL

1T

—

ns

1. In the formulas listed, T = the clock cycle. For 80MHz operation, T = 12.5ns.

2. Parameters listed are guaranteed by design.

Timer Inputs

P_INHL

P_IN

Timer Outputs

P_OUTHL

P_OUT

Figure 3-23 Timer Timing

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

41

3.9 Quadrature Decoder Timing

1, 2

Table 3-14 Quadrature Decoder Timing

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6 V, T_A= –40° to +85°C, C_L≤ 50pF, f_OP= 80MHz

Characteristic

Quadrature input period

Symbol

P_IN

Min

Max

—

Unit

ns

8T + 12

4T + 6

2T + 3

Quadrature input high/low period

Quadrature phase period

P_HL

—

ns

P_PH

—

ns

1. In the formulas listed, T = the clock cycle. For 80MHz operation, T=12.5ns. V_SS= 0V, V_DD= 3.0–3.6V,

T_A= –40° to +85°C, C_L≤ 50pF.

2. Parameters listed are guaranteed by design.

P_PHP_PHP_PHP_PH

Phase A

(Input)

P_HL

P_IN

P_HL

Phase B

P_HL

(Input)

P_IN

P_HL

Figure 3-24 Quadrature Decoder Timing

56F807 Technical Data Technical Data, Rev. 15

42

Freescale Semiconductor

Serial Communication Interface (SCI) Timing

3.10 Serial Communication Interface (SCI) Timing

4

Table 3-15 SCI Timing

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6 V, T_A= –40° to +85°C, C_L≤ 50pF, f_OP= 80MHz

Characteristic

Symbol

Min

—

Max

Unit

Baud Rate¹

BR

(f_MAX*2.5)/(80)

Mbps

RXD²Pulse Width

TXD³Pulse Width

RXD_PW

TXD_PW

0.965/BR

1.04/BR

ns

0.965/BR

1. f_MAXis the frequency of operation of the system clock in MHz.

2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

4. Parameters listed are guaranteed by design.

RXD

SCI receive

data pin

RXD_PW

(Input)

Figure 3-25 RXD Pulse Width

TXD

SCI receive

data pin

TXD_PW

(Input)

Figure 3-26 TXD Pulse Width

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

43

3.11 Analog-to-Digital Converter (ADC) Characteristics

Table 3-16 ADC Characteristics

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6 V, V_REF= V_DD-0.3V, ADCDIV = 4, 9, or 14, (for optimal performance),

ADC clock = 4MHz, 3.0–3.6 V, T_A= –40° to +85°C, C_L≤ 50pF, f_OP= 80MHz

Characteristic

ADC input voltages

Symbol

Min

Typ

Max

Unit

2

0¹

12

—

V_REF

V_ADCIN

—

V

Resolution

R_ES

INL

—

12

Bits

Integral Non-Linearity³

Differential Non-Linearity

LSB⁴

+/- 2.5

+/- 0.9

+/- 4

+/- 1

DNL

Monotonicity

GUARANTEED

—

ADC internal clock⁵

Conversion range

f_ADIC

R_AD

t_ADC

0.5

V_SSA

—

5

MHz

V

—

6

V_DDA

—

t_AICcycles⁶

Conversion time

Sample time

t_ADS

—

1

—

pF⁶

—

Input capacitance

C_ADI

E_GAIN

THD

—

0.93

60

5

1.00

64

—

1.08

—

Gain Error (transfer gain)⁵

Total Harmonic Distortion⁵

Offset Voltage⁵

V_OFFSET

SINAD

ENOB

SFDR

-90

55

-25

60

+10

—

mV

—

Signal-to-Noise plus Distortion⁵

Effective Number of Bits⁵

9

10

—

bit

Spurious Free Dynamic Range⁵

Bandwidth

65

70

—

dB

BW

—

100

50

—

KHz

mA

ADC Quiescent Current (each dual ADC)

I_ADC

V_REFQuiescent Current (each dual ADC)

I_VREF

—

12

16.5

mA

1. For optimum ADC performance, keep the minimum V_ADCINvalue > 25mV. Inputs less than 25mV may convert to a digital

output code of 0.

2. V_REFmust be equal to or less than V_DDAand must be greater than 2.7V. For optimal ADC performance, set V_REFto

V

_DDA-0.3V.

3. Measured in 10-90% range.

4. LSB = Least Significant Bit.

5. Guaranteed by characterization.

6. t_AIC= 1/f_ADIC

56F807 Technical Data Technical Data, Rev. 15

44

Freescale Semiconductor

Controller Area Network (CAN) Timing

.

ADC analog input

3

1

2

4

1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)

2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)

3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)

4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at

sampling time. (1pf)

Figure 3-27 Equivalent Analog Input Circuit

3.12 Controller Area Network (CAN) Timing

2

Table 3-17 CAN Timing

DD

Operating Conditions: V = V

= 0 V, V = V

= 3.0–3.6 V, T = –40° to +85°C, C < 50pF, MSCAN Clock = 30MHz

SS

SSA

DDA A L

Characteristic

Symbol

BR_CAN

Min

—

5

Max

Unit

Baud Rate

Bus Wakeup detection ¹

1

Mbps

T _WAKEUP

μs

—

1. If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any bus event

(on MSCAN_RX pin) whose duration is less than 5 microseconds is filtered away. However, a valid CAN bus wakeup detection

takes place for a wakeup pulse equal to or greater than 5 microseconds. The number 5 microseconds originates from the fact

that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps.

2. Parameters listed are guaranteed by design

MSCAN_RX

CAN receive

data pin

T _WAKEUP

(Input)

Figure 3-28 Bus Wakeup Detection

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

45

3.13 JTAG Timing

1, 3

Table 3-18 JTAG Timing

Operating Conditions: V_SS= V_SSA= 0 V, V_DD= V_DDA= 3.0–3.6 V, T_A= –40° to +85°C, C_L≤ 50pF, f_OP= 80MHz

Characteristic

TCK frequency of operation²

Symbol

Min

Max

Unit

f_OP

DC

10

MHz

TCK cycle time

t_CY

t_PW

t_DS

100

50

—

ns

TCK clock pulse width

TMS, TDI data set-up time

TMS, TDI data hold time

TCK low to TDO data valid

TCK low to TDO tri-state

TRST assertion time

DE assertion time

0.4

1.2

—

t_DH

—

t_DV

26.6

23.5

—

t_TS

—

t_TRST

t_DE

50

4T

—

1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation,

T = 12.5ns.

2. TCK frequency of operation must be less than 1/8 the processor rate.

3. Parameters listed are guaranteed by design.

t_CY

t_PW

V_IH

V_M

TCK

(Input)

V_IL

V_M= V_IL+ (V_IH– V_IL)/2

Figure 3-29 Test Clock Input Timing Diagram

56F807 Technical Data Technical Data, Rev. 15

46

Freescale Semiconductor

JTAG Timing

TCK

(Input)

t_DS

t_DH

TDI

TMS

Input Data Valid

(Input)

t_DV

TDO

(Output)

Output Data Valid

t_TS

TDO

(Output)

t_DV

TDO

(Output)

Output Data Valid

Figure 3-30 Test Access Port Timing Diagram

TRST

(Input)

t_TRST

Figure 3-31 TRST Timing Diagram

DE

t_DE

Figure 3-32 OnCE—Debug Event

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

47

Part 4 Packaging

4.1 Package and Pin-Out Information 56F807

This section contains package and pin-out information for the 56F807. This device comes in two case

types: low-profile quad flat pack (LQFP) or mold array process ball grid assembly (MAPBGA).

Figure 4-1 shows the package outline for the LQFP case, Figure 4-2 shows the mechanical parameters

for the LQFP case, and Table 4-1 lists the pinout for the LQFP case. Figure 4-3 shows the mechanical

parameters for the MAPBGA case, and Table 4-2 lists the pinout for the MAPBGA package.

Orientation Mark

A0

ANB7

A1

A2

A3

A4

A5

ANB6

ANB5

ANB4

ANB3

121

Pin 1

ANB2

A6

A7

ANB1

ANB0

V

DD

A8

SSA

V

DDA

A9

REF2

A10

ANA7

A11

A12

ANA6

ANA5

A13

A14

ANA4

ANA3

A15

ANA2

ANA1

ANA0

V

SS

PS

DS

WR

RD

D0

V

SSA

V

DDA

REF

RESET

RSTO

D1

V

D2

D3

DD

V

SS

DD

D4

D5

EXTAL

XTAL

D6

D7

V

SS

D8

SS

D9

V

DD

D10

DDA

V

DD

SSA

D11

D12

D13

EXTBOOT

FAULTA3

FAULTA2

D14

D15

81

FAULTA1

FAULTA0

PWMA5

41

GPIOB0

Figure 4-1 Top View, 56F807 160-pin LQFP Package

56F807 Technical Data Technical Data, Rev. 15

48

Freescale Semiconductor

Package and Pin-Out Information 56F807

160X

0.20 C A-B D

D

b

GG

D

2

6

D

(b)

SECTION G-G

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DATUMS A, B, AND D TO BE DETERMINED

WHERETHE LEADSEXITTHEPLASTICBODY

AT DATUM PLANE H.

4. DIMENSIONS D1 AND E1 DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE

PROTRUSION IS 0.25mm PER SIDE.

DIMENSIONS D1 AND E1 ARE MAXIMUM

PLASTIC BODY SIZE DIMENSIONS

INCLUDING MOLD MISMATCH.

D1

2

5. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL NOT CAUSE THE LEAD

WIDTH TO EXCEED THE MAXIMUM b

DIMENSION BY MORE THAN 0.08mm.

DAMBAR CAN NOT BE LOCATED ON THE

LOWER RADIUS OR THE FOOT. MINIMUM

SPACE BETWEEN A PROTRUSION AND AN

ADJACENT LEAD IS 0.07mm.

D1

4X

0.20 H A-B D

DETAIL F

6. EXACT SHAPE OF CORNERS MAY VARY.

0.08 C

156X e

C

MILLIMETERS

DIM MIN MAX

4X e/2

SEATING

PLANE

160X e

A

A1

A2

b

b1

c

c1

D

D1

e

---

0.05

1.35

0.17

0.09

1.60

0.15

1.45

0.27

0.23

0.20

0.16

M

0.08

C A-B D

θ2

θ1

H

26.00 BSC

24.00 BSC

0.50 BSC

R1

R2

E

E1

L

26.00 BSC

24.00 BSC

0.45

0.75

L1

R1

R2

S

1.00 REF

θ3

0.25

0.08

0.20

---

0.20

---

θ

GAGE

PLANE

S

L

(L1)

θ

0

11

7

---

13

°

θ 1

θ 2

θ 3

°

DETAIL F

CASE 1259-01

ISSUE O

Figure 4-2 160-pin LQFP Mechanical Information

Please see www.freescale.com for the most current case outline.

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

49

Table 4-1 56F807 LQFP Package Pin Identification by Pin Number

Pin No. Signal Name Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

1

2

A0

A1

41

42

GPIOB1

GPIOB2

81

82

PWMA5

121

122

DE

FAULTA0

V_SS

3

4

5

6

7

A2

A3

A4

A5

A6

43

44

45

46

47

GPIOB3

GPIOB4

GPIOB5

GPIOB6

GPIOB7

83

84

85

86

87

FAULTA1

FAULTA2

FAULTA3

EXTBOOT

V_SSA

123

124

125

126

127

ISA0

ISA1

ISA2

TD0

TD1

8

9

A7

V_DD

A8

48

49

50

51

V_SS

88

89

90

91

V_DDA

V_DD

V_SS

128

129

130

131

TD2

TD3

TC0

TC1

GPIOD0

GPIOD1

GPIOD2

10

11

A9

V_SS

12

13

14

A10

A11

A12

52

53

54

GPIOD3

GPIOD4

GPIOD5

92

93

94

XTAL

EXTAL

V_DD

132

133

134

TRST

TCS

TCK

15

16

A13

A14

55

56

TXD1

RXD1

95

96

V_SS

V_DD

135

136

TMS

TDI

17

18

A15

V_SS

57

58

PWMB0

PWMB1

97

98

RSTO

137

138

TDO

RESET

VCAPC2

19

20

PS

DS

59

60

PWMB2

PWMB3

99

VREF

V_DDA

139

140

MSCAN_TX

V_DD

100

21

WR

61

PWMB4

101

V_SSA

141

V_SS

22

23

RD

D0

62

63

PWMB5

V_DD

102

103

ANA0

ANA1

142

143

MSCAN_RX

SS

24

25

26

27

28

29

30

D1

D2

D3

D4

D5

D6

D7

64

65

66

67

68

69

70

ISB0

VCAPC1

ISB1

104

105

106

107

108

109

110

ANA2

ANA3

ANA4

ANA5

ANA6

ANA7

VREF2

144

145

146

147

148

149

150

SCLK

MISO

MOSI

ISB2

PHA0

VPP2

IRQA

PHB0

INDEX0

HOME0

IRQB

56F807 Technical Data Technical Data, Rev. 15

50

Freescale Semiconductor

Package and Pin-Out Information 56F807

Table 4-1 56F807 LQFP Package Pin Identification by Pin Number (Continued)

Pin No. Signal Name Pin No.

Signal Name

FAULTB0

FAULTB1

FAULTB2

FAULTB3

Pin No.

111

Signal Name

V_DDA

Pin No.

151

Signal Name

PHA1

31

32

33

34

D8

D9

71

72

73

74

112

V_SSA

152

PHB1

D10

V_DD

113

ANB0

153

V_DD

114

ANB1

154

INDEX1

35

36

D11

D12

75

76

PWMA0

V_SS

115

116

ANB2

ANB3

155

156

HOME1

VPP

37

D13

77

PWMA1

117

ANB4

157

V_SS

38

39

40

D14

D15

78

79

80

PWMA2

PWMA3

PWMA4

118

119

120

ANB5

ANB6

ANB7

158

159

160

CLKO

TXD0

RXD0

GPIOB0

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

51

D

X

LASER MARK FOR PIN 1

IDENTIFICATION IN

THIS AREA

Y

M

K

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND

TOLERANCES PER ASME Y14.5M, 1994.

3. DIMENSION b IS MEASURED AT THE

MAXIMUM SOLDER BALL DIAMETER,

PARALLEL TO DATUM PLANE Z.

4. DATUM Z (SEATING PLANE) IS DEFINED BY

THE SPHERICAL CROWNS OF THE SOLDER

BALLS.

E

5. PARALLELISM MEASUREMENT SHALL

EXCLUDE ANY EFFECT OF MARK ON TOP

SURFACE OF PACKAGE.

MILLIMETERS

DIM MIN MAX

0.20

A

A1

A2

b

1.32

0.27

1.18 REF

1.75

0.47

0.35

0.65

13X

e

D

E

e

15.00 BSC

1.00 BSC

0.50 BSC

S

METALIZED MARK FOR

PIN 1 IDENTIFICATION

IN THIS AREA

S

14 13 12 11 10

9

6

5

4

3

2

1

A

B

C

D

E

F

5

S

0.30 Z

A2

13X

e

A

G

H

J

160X

A1

0.15 Z

4

Z

K

L

M

DETAIL K

ROTATED 90 CLOCKWISE

°

N

P

3

160X

b

0.30 Z X Y

0.10 Z

VIEW M-M

CASE 1268-01

ISSUE O

Figure 4-3 160 MAPBGA Mechanical Information

Please see www.freescale.com for the most current case outline.

56F807 Technical Data Technical Data, Rev. 15

52

Freescale Semiconductor

Package and Pin-Out Information 56F807

Table 4-2 160 MAPBGA Package Pin Identification by Pin Number

Solder

Ball

Solder

Ball

Solder

Ball

Solder

Ball

Signal Name

C3

B2

D3

C2

B1

A0

A1

A2

A3

A4

N4

P4

M4

L5

GPIOB5

GPIOB6

GPIOB7

V_SS

K12

K13

L14

K11

K14

E10

D9

B9

E9

A9

TC1

TRST

TCS

TCK

TMS

V_SSA

V_DDA

V_DD

V_SS

N5

GPIOD0

V_SS

D2

C1

D1

A5

A6

A7

P5

K5

N6

GPIOD1

GPIOD2

GPIOD3

J13

J12

J14

XTAL

EXTAL

V_DD

D8

B8

A8

TDI

TDO

VCAPC2

E3

E2

E1

L6

K6

P6

GPIOD4

GPIOD5

TXD1

J11

H13

H12

E8

D7

E7

MSCAN_TX

V_DD

A8

V_SS

V

DD

A9

RSTO

V_SS

F3

F2

F1

A10

A11

A12

N7

L7

P7

RXD1

H14

H11

G12

RESET

VREF

V_DDA

D6

H1

H2

MSCAN_RX

PWMB0

PWMB1

D1

D2

G3

A13

K7

PWMB2

G11

J3

D3

V_SSA

G2

G1

F4

A14

A15

V_SS

L8

K8

P8

PWMB3

PWMB4

PWMB5

G14

B13

A14

ANA0

DE

J1

J2

K3

D4

D5

D6

V_SS

G4

PS

L9

B12

ISA0

K1

D7

V_DD

H4

J4

DS

WR

RD

N8

ISB0

A13

A12

B11

ISA1

ISA2

TD0

L1

K2

L3

D8

D9

P14

M13

PWMA5

FAULTA0

K4

D10

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

53

Table 4-2 160 MAPBGA Package Pin Identification by Pin Number (Continued)

Solder

Ball

Solder

Ball

Solder

Ball

Solder

Ball

Signal Name

P1

GPIOB1

L12

FAULTA1

A11

TD1

M1

V_DD

N3

P2

P3

N2

GPIOB2

GPIOB3

GPIOB4

D14

N14

L13

M14

N11

FAULTA2

FAULTA3

EXTBOOT

V_SS

D10

B10

A10

D14

TD2

TD3

TC0

L2

N1

M2

D5

D11

D12

D13

PHB0

V_SSA

M3

L4

D15

GPIOB0

VCAPC1

ISB1

P13

N12

N13

M12

F11

PWMA1

PWMA2

PWMA3

PWMA4

ANA1

D11

D12

D13

C14

C13

ANA8

ANA9

B6

A5

E4

B5

A4

INDEX0

HOME0

PHA1

PHB1

V_DD

K10

K9

ANA10

ANA11

ANA12

P9

ISB2

L10

N9

VPP2

IRQA

G13

F12

F14

E11

F13

E12

E14

ANA2

ANA3

ANA4

ANA5

ANA6

ANA7

VREF2

C11

B14

C12

A7

ANA13

ANA14

ANA15

SS

D4

C4

B4

A2

B3

A1

A3

INDEX1

HOME1

VPP

P10

P11

N10

L11

M11

IRQB

FAULTB0

FAULTB1

FAULTB2

FAULTB3

CLKO

TXD0

RXD0

V_SS

E5

SCLK

MISO

MOSI

B7

A6

P12

PWMA0

E13

E6

PHA0

H3

D0

V_DDA

56F807 Technical Data Technical Data, Rev. 15

54

Freescale Semiconductor

Thermal Design Considerations

Part 5 Design Considerations

5.1 Thermal Design Considerations

An estimation of the chip junction temperature, T , in °C can be obtained from the equation:

J

Equation 1: T_J= T_A+ (P_D× R_θJA

)

Where:

T_A= ambient temperature °C

R_θJA= package junction-to-ambient thermal resistance °C/W

P_D= power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and

a case-to-ambient thermal resistance:

Equation 2: R_θJA= R_θJC+ R_θCA

Where:

R_θJA= package junction-to-ambient thermal resistance °C/W

R_θJC= package junction-to-case thermal resistance °C/W

R_θCA= package case-to-ambient thermal resistance °C/W

R

is device-related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

θCA

the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or

otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This

model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through

the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where

the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the

device thermal performance may need the additional modeling capability of a system level thermal

simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which

the package is mounted. Again, if the estimations obtained from R

the thermal performance is adequate, a system level model may be appropriate.

do not satisfactorily answer whether

θJA

Definitions:

A complicating factor is the existence of three common definitions for determining the junction-to-case

thermal resistance in plastic packages:

•

Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the

chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation

across the surface.

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

55

•

Measure the thermal resistance from the junction to where the leads are attached to the case. This definition

is approximately equal to a junction to board thermal resistance.

Use the value obtained by the equation (T_J– T_T)/P_Dwhere T_Tis the temperature of the package case

determined by a thermocouple.

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T

thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so

that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire

is placed flat against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the

interface between the case of the package and the interface material. A clearance slot or hole is normally

required in the heat sink. Minimizing the size of the clearance is important to minimize the change in

thermal performance caused by removing part of the thermal interface to the heat sink. Because of the

experimental difficulties with this technique, many engineers measure the heat sink temperature and then

back-calculate the case temperature using a separate measurement of the thermal resistance of the

interface. From this case temperature, the junction temperature is determined from the junction-to-case

thermal resistance.

5.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to guard

against damage due to high static voltage or electrical

fields. However, normal precautions are advised to

avoid application of any voltages higher than maximum

rated voltages to this high-impedance circuit. Reliability

of operation is enhanced if unused inputs are tied to an

appropriate voltage level.

Use the following list of considerations to assure correct operation:

•

Provide a low-impedance path from the board power supply to each V_DDpin on the controller, and from the

board ground to each V_SSpin.

•

The minimum bypass requirement is to place 0.1 μF capacitors positioned as close as possible to the

package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of

the V_DD/V_SSpairs, including V_DDA/V_SSA.Ceramic and tantalum capacitors tend to provide better

performance tolerances.

56F807 Technical Data Technical Data, Rev. 15

56

Freescale Semiconductor

Electrical Design Considerations

•

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V_DDand V_SSpins

are less than 0.5 inch per capacitor lead.

Bypass the V_DDand V_SSlayers of the PCB with approximately 100 μF, preferably with a high-grade

capacitor such as a tantalum capacitor.

•

Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.

This is especially critical in systems with higher capacitive loads that could create higher transient currents

in the V_DDand V_SScircuits.

•

Take special care to minimize noise levels on the VREF, V_DDAand V_SSApins.

Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or

debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means

to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs

that do not require debugging functionality, such as consumer products, TRST should be tied low.

•

Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an

interface to this port to allow in-circuit Flash programming.

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

57

Part 6 Ordering Information

Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor

sales office or authorized distributor to determine availability and to order parts.

Table 6-1 56F807 Ordering Information

Ambient

Frequency

(MHz)

Supply

Voltage

Count

Part

Package Type

Order Number

56F807

3.0–3.6 V

Low-Profile Quad Flat Pack (LQFP)

160

80

DSP56F807PY80

DSP56F807VF80

Mold Array Process Ball Grid Array

(MAPBGA)

56F807

3.0–3.6 V

Low-Profile Quad Flat Pack (LQFP)

160

80

DSP56F807PY80E*

DSP56F807VF80E*

Mold Array Process Ball Grid Array

(MAPBGA)

*This package is RoHS compliant.

56F807 Technical Data Technical Data, Rev. 15

58

Freescale Semiconductor

Electrical Design Considerations

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

59

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

support@freescale.com

USA/Europe or Locations Not Listed:

Freescale Semiconductor

Technical Information Center, CH370

1300 N. Alma School Road

Chandler, Arizona 85224

+1-800-521-6274 or +1-480-768-2130

support@freescale.com

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

support@freescale.com

RoHS-compliant and/or Pb-free versions of Freescale products have the

functionality and electrical characteristics of their non-RoHS-compliant

and/or non-Pb-free counterparts. For further information, see

http://www.freescale.com or contact your Freescale sales representative.

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

For information on Freescale’s Environmental Products program, go to

http://www.freescale.com/epp.

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064, Japan

0120 191014 or +81 3 5437 9125

support.japan@freescale.com

Information in this document is provided solely to enable system and

software implementers to use Freescale Semiconductor products. There are

no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits or integrated circuits based on the

information in this document.

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Technical Information Center

2 Dai King Street

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+800 2666 8080

Freescale Semiconductor reserves the right to make changes without further

notice to any products herein. Freescale Semiconductor makes no warranty,

representation or guarantee regarding the suitability of its products for any

particular purpose, nor does Freescale Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or

incidental damages. “Typical” parameters that may be provided in Freescale

Semiconductor data sheets and/or specifications can and do vary in different

applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer

application by customer’s technical experts. Freescale Semiconductor does

not convey any license under its patent rights nor the rights of others.

Freescale Semiconductor products are not designed, intended, or authorized

for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other

application in which the failure of the Freescale Semiconductor product could

create a situation where personal injury or death may occur. Should Buyer

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or unauthorized application, Buyer shall indemnify and hold Freescale

Semiconductor and its officers, employees, subsidiaries, affiliates, and

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personal injury or death associated with such unintended or unauthorized

use, even if such claim alleges that Freescale Semiconductor was negligent

regarding the design or manufacture of the part.

support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

1-800-441-2447 or 303-675-2140

Fax: 303-675-2150

LDCForFreescaleSemiconductor@hibbertgroup.com

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor,

Inc. All other product or service names are the property of their respective owners.

This product incorporates SuperFlash® technology licensed from SST.

DSP56F807

Rev. 15

01/2007

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		控制器
页数	文件大小	规格书
60页	874K
描述
16-bit Digital Signal Controllers

型号	品牌	描述	获取价格	数据表
56F807_1	FREESCALE	16-bit Digital Signal Controllers	获取价格
56F807E	FREESCALE	16-bit Digital Signal Controllers	获取价格
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