SEMICONDUCTOR TECHNICAL DATA
The MC74VHC373 is an advanced high speed CMOS octal latch with
3–state output fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
This 8–bit D–type latch is controlled by a latch enable input and an output
enable input. When the output enable input is high, the eight outputs are in a
high impedance state.
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
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•
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•
•
•
•
•
•
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•
High Speed: t
= 5.0ns (Typ) at V
= 5V
PD
Low Power Dissipation: I
CC
= 4µA (Max) at T = 25°C
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
CC
A
High Noise Immunity: V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
= V
= 28% V
NIH
NIL CC
Designed for 2V to 5.5V Operating Range
Low Noise: V
= 0.9V (Max)
OLP
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 186 FETs or 46.5 Equivalent Gates
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
ORDERING INFORMATION
MC74VHCXXXDW
MC74VHCXXXDT
MC74VHCXXXM
SOIC
TSSOP
SOIC EIAJ
LOGIC DIAGRAM
2
5
3
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
PIN ASSIGNMENT
6
7
1
20
V
OE
Q0
D0
D1
CC
8
9
DATA
INPUTS
NONINVERTING
OUTPUTS
2
3
4
19
18
17
Q7
D7
D6
13
12
15
16
19
14
17
18
D5
D6
D7
Q1
Q2
5
16
15
14
13
12
11
Q6
Q5
D5
D4
Q4
6
D2
7
11
1
D3
8
LE
OE
Q3
9
GND
10
LE
FUNCTION TABLE
INPUTS
OUTPUT
Q
OE
LE
D
L
L
L
H
H
L
H
L
X
X
H
L
No Change
Z
H
X
6/97
REV 1
1
Motorola, Inc. 1997