IDT54/74FCT162245T/AT/CT
FASTCMOS16-BITBIDIRECTIONALTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
ΔICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V
—
0.5
1.5
mA
(3)
ICCD
IC
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
xOE = xDIR = GND
One Input Toggling
50% Duty Cycle
VIN = VCC
VIN = GND
—
60
100
µ A /
MHz
Total Power Supply Current(6)
VCC = Max.
Outputs Open
fi = 10MHz
VIN = VCC
VIN = GND
—
—
—
—
0.6
0.9
2.4
6.4
1.5
2.3
mA
50% Duty Cycle
xOE = xDIR = GND
One Bits Togging
VIN = 3.4V
VIN = GND
(5)
VCC = Max.
Outputs Open
fi = 2.5MHz
VIN = VCC
VIN = GND
4.5
50% Duty Cycle
xOE = xDIR = GND
Sixteen Bits Togging
VIN = 3.4V
VIN = GND
16.5(5
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
54FCT162445T
Mil.
54/74FCT162245AT
Ind. Mil.
Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
54/74FCT162245CT
Ind. Mil.
Symbol
tPLH
Parameter
Condition(1)
CL = 50pF
RL = 500Ω
Min.(2)
Max.
PropagationDelay
A to B, B to A
1.5
1.5
1.5
1.5
1.5
—
7.5
1.5
1.5
1.5
1.5
1.5
—
4.6
6.2
5
1.5
1.5
1.5
1.5
1.5
—
4.9
6.5
6
1.5
1.5
1.5
1.5
1.5
—
3.5
4.4
4
1.5
1.5
1.5
1.5
1.5
—
4.5
6.2
5.2
6.2
5.2
0.5
ns
ns
ns
ns
ns
ns
tPHL
tPZH
tPZL
OutputEnableTime
10
10
10
10
0.5
xOE to A or B
tPHZ
tPLZ
OutputDisableTime
xOE to A or B
tPZH
tPZL
OutputEnableTime
6.2
5
6.5
6
4.8
4
(4)
xDIR to A or B
tPHZ
tPLZ
OutputDisableTime
(4)
xDIR to A or B
(3)
tSK(o)
OutputSkew
0.5
0.5
0.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
4