Connection Diagrams
Pin Assignment
Pin Assignment for LCC
for DIP and Flatpak
DS100254-4
DS100254-2
Functional Description
The ’ACT825 consists of eight D-type edge-triggered
flip-flops. These devices have TRI-STATE® outputs for bus
systems, organized in a broadside pinning. In addition to the
clock and output enable pins, the buffered clock (CP) and
buffered Output Enable (OE) are common to all flip-flops.
The flip-flops will store the state of their individual D inputs
that meet the setup and hold time requirements on the
LOW-to-HIGH CP transition. With OE1, OE2 and OE3 LOW,
the contents of the flip-flops are available at the outputs.
When one of OE1, OE2 or OE3 is HIGH, the outputs go to the
high impedance state.
Operation of the OE input does not affect the state of the
flip-flops. The ’ACT825 has Clear (CLR) and Clock Enable
(EN) pins. These pins are ideal for parity bus interfacing in
high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When EN is
HIGH, the outputs do not change state, regardless of the
data or clock input transitions.
Function Table
Inputs
Internal
Output
Function
OE
H
H
H
L
CLR
X
EN
L
CP
N
N
Dn
L
Q
L
O
Z
High-Z
X
L
H
X
X
X
X
L
H
Z
High-Z
Clear
Clear
Hold
L
X
X
H
H
L
X
X
L
Z
L
L
L
H
L
H
X
NC
NC
L
Z
H
X
NC
Z
Hold
N
N
N
N
H
H
L
H
Load
Load
Load
Load
H
L
H
L
H
Z
H
L
L
L
L
H
L
H
H
H
=
=
=
=
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
N =
LOW-to-HIGH Transition
=
NC No Change
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