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54ACT823SDMQR

更新时间： 2024-02-13 22:35:08

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器
页数	文件大小	规格书
8页	150K
描述
9-Bit D Flip-Flop

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技术参数
数据手册

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54ACT823SDMQR 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.73
Is Samacsys：	N	Base Number Matches：	1

54ACT823SDMQR 数据手册

Functional Description

The ’ACT823 consists of nine D-type edge-triggered flip-

flops. These have TRI-STATE outputs for bus systems or-

ganized with inputs and outputs on opposite sides. The buff-

ered clock (CP) and buffered Output Enable (OE) are com-

mon to all flip-flops. The flip-flops will store the state of their

individual D inputs that meet the setup and hold time re-

quirements on the LOW-to-HIGH CP transition. With OE

LOW, the contents of the flip-flops are available at the out-

puts. When OE is HIGH, the outputs go to the high imped-

ance state. Operation of the OE input does not affect

the state of the flip-flops. In addition to the Clock and Output

Enable pins, there are Clear (CLR) and Clock Enable (EN)

pins. These devices are ideal for parity bus interfacing in

high performance systems.

When CLR is LOW and OE is LOW, the outputs are LOW.

When CLR is HIGH, data can be entered into the flip-flops.

When EN is LOW, data on the inputs is transferred to the

outputs on the LOW-to-HIGH clock transition. When the EN

is HIGH, the outputs do not change state, regardless of the

data or clock input transitions.

Function Table

Inputs

Internal

Output

Function

CLR

High Z

Clear

Hold

Load

HIGH Voltage Level

LOW Voltage Level

Immaterial

High Impedance

LOW-to-HIGH Transition

No Change

Logic Diagram

TL/F/9894–5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

123 4 5 6 7 8

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