Datasheet > 54ACT74DM

54ACT74DM

更新时间： 2024-01-28 06:05:34

品牌	Logo	应用领域
德州仪器 - TI		输出元件逻辑集成电路触发器
页数	文件大小	规格书
8页	180K
描述
ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14

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54ACT74DM 技术参数

生命周期：	Obsolete	包装说明：	DIP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.58	系列：	ACT
JESD-30 代码：	R-GDIP-T14	长度：	19.43 mm
逻辑集成电路类型：	D FLIP-FLOP	位数：	1
功能数量：	2	端子数量：	14
最高工作温度：	125 °C	最低工作温度：	-55 °C
输出极性：	COMPLEMENTARY	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	传播延迟（tpd）：	14 ns
认证状态：	Not Qualified	座面最大高度：	5.08 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	MILITARY
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	触发器类型：	POSITIVE EDGE
宽度：	7.62 mm	最小 fmax：	85 MHz
Base Number Matches：	1

54ACT74DM 数据手册

July 2003

54AC74/54ACT74

Dual D-Type Positive Edge-Triggered Flip-Flop

Clear and Set are independent of clock

General Description

Simultaneous LOW on C_Dand S_Dmakes both Q and Q

HIGH

The ’AC/’ACT74 is a dual D-type flip-flop with Asynchronous

Clear and Set inputs and complementary (Q, Q) outputs.

Information at the input is transferred to the outputs on the

positive edge of the clock pulse. Clock triggering occurs at a

voltage level of the clock pulse and is not directly related to

the transition time of the positive-going pulse. After the Clock

Pulse input threshold voltage has been passed, the Data

input is locked out and information present will not be trans-

ferred to the outputs until the next rising edge of the Clock

Pulse input.

Features

n I_CCreduced by 50%

n Output source/sink 24 mA

n ’ACT74 has TTL-compatible inputs

n Standard Microcircuit Drawing (SMD)

— ’AC74: 5962-88520

— ’ACT74: 5962-87525

n 54AC74 now qualified to 300Krad RHA designation,

refer to the SMD for more information

Asynchronous Inputs:

LOW input to S_D(Set) sets Q to HIGH level

LOW input to C_D(Clear) sets Q to LOW level

Logic Symbols

10026602

10026601

IEEE/IEC

Pin Names

Description

Data Inputs

D₁, D₂

CP₁, CP₂

_D1, C_D2

_D1, S_D2

Q₁, Q₁, Q₂, Q₂

Clock Pulse Inputs

Direct Clear Inputs

Direct Set Inputs

Outputs

10026603

FACT^®is a registered trademark of Fairchild Semiconductor Corporation.

DS100266

www.national.com

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