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54ACT573FM PDF预览

54ACT573FM

更新时间: 2024-01-26 08:55:47
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
13页 215K
描述
ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20, CERAMIC, FP-20

54ACT573FM 技术参数

生命周期:Transferred包装说明:DFP, FL20,.3
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.66其他特性:BROADSIDE VERSION OF 373
系列:ACTJESD-30 代码:R-GDFP-F20
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装等效代码:FL20,.3
封装形状:RECTANGULAR封装形式:FLATPACK
电源:5 VProp。Delay @ Nom-Sup:13.5 ns
传播延迟(tpd):13 ns认证状态:Not Qualified
座面最大高度:2.286 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL宽度:6.731 mm
Base Number Matches:1

54ACT573FM 数据手册

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Functional Description  
Truth Table  
The ’ACT573 contains eight D-type latches with TRI-STATE  
output buffers. When the Latch Enable (LE) input is HIGH,  
data on the Dn inputs enters the latches. In this condition the  
latches are transparent, i.e., a latch output will change state  
each time its D input changes. When LE is LOW the latches  
store the information that was present on the D inputs a  
setup time preceding the HIGH-to-LOW transition of LE. The  
TRI-STATE buffers are controlled by the Output Enable (OE)  
input. When OE is LOW, the buffers are enabled. When OE  
is HIGH the buffers are in the high impedance mode but this  
does not interfere with entering new data into the latches.  
Inputs  
Outputs  
OE  
L
LE  
H
H
L
D
H
L
On  
H
L
L
L
X
X
O0  
Z
H
X
=
=
=
=
H
L
Z
X
O
HIGH Voltage  
LOW Voltage  
High Impedance  
Immaterial  
=
Previous O before HIGH-to-LOW transition of Latch Enable  
0
0
Logic Diagram  
DS100332-5  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
3
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