54ACT253L

更新时间： 2024-01-10 11:28:04

品牌	Logo	应用领域
美国国家半导体 - NSC		复用器
页数	文件大小	规格书
8页	156K
描述
Dual 4-Input Multiplexer with TRI-STATE Outputs

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技术参数
数据手册

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54ACT253L 技术参数

生命周期：	Obsolete	包装说明：	DIE,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.72	系列：	ACT
JESD-30 代码：	X-XUUC-N16	逻辑集成电路类型：	MULTIPLEXER
功能数量：	2	输入次数：	4
输出次数：	1	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-55 °C
输出特性：	3-STATE	输出极性：	TRUE
封装主体材料：	UNSPECIFIED	封装代码：	DIE
封装形状：	UNSPECIFIED	封装形式：	UNCASED CHIP
传播延迟（tpd）：	18.5 ns	认证状态：	Not Qualified
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	NO LEAD	端子位置：	UPPER
Base Number Matches：	1

54ACT253L 数据手册

Connection Diagrams

Pin Assignment

for DIP and Flatpak

Pin Assignment

for LCC

DS100285-3

DS100285-4

Functional Description

The ’AC/’ACT253 contains two identical 4-input multiplexers

with TRI-STATE outputs. They select two bits from four

sources selected by common Select inputs (S₀, S₁). The

4-input multiplexers have individual Output Enable (OE_a,

OE_b) inputs which, when HIGH, force the outputs to a high

impedance (High Z) state. This device is the logic implemen-

tation of a 2-pole, 4-position switch, where the position of the

switch is determined by the logic levels supplied to the two

select inputs. The logic equations for the outputs are shown:

I_2a• S₁• S₀+ I_3a• S₁• S₀)

Z_bOE_b• (I_0b• S₁• S₀+ I_1b• S₁• S₀

I_2b• S₁• S₀+ I_3b• S₁• S₀)

If the outputs of TRI-STATE devices are tied together, all but

one device must be in the high impedance state to avoid

high currents that would exceed the maximum ratings. De-

signers should ensure that Output Enable signals to

TRI-STATE devices whose outputs are tied together are de-

signed so that there is no overlap.

Z_aOE_a• (I_0a• S₁• S₀+ I_1a• S₁• S₀

Truth Table

Select

Inputs

Data Inputs

Output

Outputs

Enable

S₀

S₁

I₀

I₁

I₂

I₃

Address Inputs S and S are common to both sections.

HIGH Voltage Level

LOW Voltage Level

Immaterial

High Impedance

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