Datasheet > 54ACT163LM

54ACT163LM

更新时间： 2024-02-01 09:01:28

品牌	Logo	应用领域
德州仪器 - TI		逻辑集成电路触发器
页数	文件大小	规格书
10页	202K
描述
ACT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CQCC20, CERAMIC, LCC-20

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54ACT163LM 技术参数

生命周期：	Transferred	包装说明：	QCCN,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.64	计数方向：	UP
系列：	ACT	JESD-30 代码：	S-CQCC-N20
长度：	8.89 mm	负载/预设输入：	YES
逻辑集成电路类型：	BINARY COUNTER	工作模式：	SYNCHRONOUS
位数：	4	功能数量：	1
端子数量：	20	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	QCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER	传播延迟（tpd）：	10.5 ns
认证状态：	Not Qualified	座面最大高度：	1.905 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	NO LEAD	端子节距：	1.27 mm
端子位置：	QUAD	触发器类型：	POSITIVE EDGE
宽度：	8.89 mm	最小 fmax：	90 MHz
Base Number Matches：	1

54ACT163LM 数据手册

Functional Description

The ’AC/’ACT163 counts in modulo-16 binary sequence.

From state 15 (HHHH) it increments to state 0 (LLLL). The

clock inputs of all flip-flops are driven in parallel through a

clock buffer. Thus all changes of the Q outputs occur as a

result of, and synchronous with, the LOW-to-HIGH transition

of the CP input signal. The circuits have four fundamental

modes of operation, in order of precedence: synchronous

reset, parallel load, count-up and hold. Four control inputsÐ

Synchronous Reset (SR), Parallel Enable (PE), Count En-

able Parallel (CEP) and Count Enable Trickle (CET)Ðdeter-

mine the mode of operation, as shown in the Mode Select

Table. A LOW signal on SR overrides counting and parallel

loading and allows all outputs to go LOW on the next rising

edge of CP. A LOW signal on PE overrides counting and

there is plenty of time for the ripple to progress through the

intermediate stages. The critical timing that limits the clock

period is the CP to TC delay of the first stage plus the CEP

to CP setup time of the last stage. The TC output is subject

to decoding spikes due to internal race conditions and is

therefore not recommended for use as a clock or asynchro-

nous reset for flip-flops, registers or counters.

Logic Equations: Count Enable

CEP CET PE

CET

Mode Select Table

Action on the Rising

CET

CEP

Clock Edge (L)

allows information on the Parallel Data (P ) inputs to be

Reset (Clear)

loaded into the flip-flops on the next rising edge of CP. With

PE and SR HIGH, CEP and CET permit counting when both

are HIGH. Conversely, a LOW signal on either CEP or CET

inhibits counting.

^{Load (P}_nx Q )

Count (Increment)

No Change (Hold)

The ’AC/’ACT163 uses D-type edge-triggered flip-flops and

changing the SR, PE, CEP and CET inputs when the CP is in

either state does not cause errors, provided that the recom-

mended setup and hold times, with respect to the rising

edge of CP, are observed.

HIGH Voltage Level

LOW Voltage Level

Immaterial

State Diagram

The Terminal Count (TC) output is HIGH when CET is HIGH

and counter is in state 15. To implement synchronous multi-

stage counters, the TC outputs can be used with the CEP

and CET inputs in two different ways.

Figure 1 shows the connections for simple ripple carry, in

which the clock period must be longer than the CP to TC

delay of the first stage, plus the cumulative CET to TC de-

lays of the intermediate stages, plus the CET to CP setup

time of the last stage. This total delay plus setup time sets

the upper limit on clock frequency. For faster clock rates,

the carry lookahead connections shown in Figure 2 are rec-

ommended. In this scheme the ripple delay through the in-

termediate stages commences with the same clock that

causes the first stage to tick over from max to min in the Up

mode, or min to max in the Down mode, to start its final

cycle. Since this final cycle takes 16 clocks to complete,

TL/F/9932–5

TL/F/9932–8

FIGURE 1

TL/F/9932–9

FIGURE 2

123 4 5 6 7...10

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与54ACT163LM相关器件

型号	品牌	描述	获取价格	数据表
54ACT163LMQB	ETC	Synchronous Up Counter	获取价格
54ACT163LMX	TI	ACT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CQCC20, CERAMIC, LCC-20	获取价格
54ACT163W-QMLV	ETC	Synchronous Up Counter	获取价格
54ACT163WRQMLV	ETC	Synchronous Up Counter	获取价格
54ACT16470	TI	16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS	获取价格
54ACT16470WD	ETC	Dual 8-bit Bus Transceiver	获取价格

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