Datasheet > 54ACT11109_09

54ACT11109_09

更新时间： 2022-10-12 16:37:56

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
5页	73K
描述
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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54ACT11109_09 数据手册

54ACT11109, 74ACT11109

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993

54ACT11109 . . . J PACKAGE

74ACT11109 . . . D OR N PACKAGE

(TOP VIEW)

• Inputs Are TTL-Voltage Compatible

• Flow-Through Architecture Optimizes

PCB Layout

• Center-Pin V

and GND Configurations

Minimize High-Speed Switching Noise

1CLK

1PRE

GND

2PRE

2CLK

• EPIC (Enhanced-Performance Implanted

CMOS) 1-µm Process

1CLR

• 500-mA Typical Latch-Up Immunity

at 125°C

2CLR

• Package Options Include Plastic

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and

Ceramic 300-mil DIPs

54ACT11109 . . . FK PACKAGE

(TOP VIEW)

description

These devices contain two independent J-K

positive-edge-triggered flip-flops. A low level at

the preset (1PRE or 2PRE) or clear (1CLR or

2CLR) input sets or resets the outputs regardless

of the levels of the other inputs. When PRE and

CLR are inactive (high), data at the J and K inputs

meeting the setup time requirements are

transferred to the outputs on the positive-going

edge of the clock pulse. Clock triggering occurs at

a voltage level and is not directly related to the rise

time of the clock pulse. Following the hold-time

interval, data at the J and K inputs may be

changed without affecting the levels at the

outputs. These versatile flip-flops can perform as

toggle flip-flops by grounding K and tying J high.

They also can perform as D-type flip-flops if J and

K are tied together.

20 19

1CLK

2CLK

2PRE

1PRE

9 10 11 12 13

NC – No internal connection

The 54ACT11109 is characterized for operation over the full military temperature range of –55°C to 125°C. The

74ACT11109 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

†

↑

Toggle

↑

†

Thisconfigurationisnonstable;thatis, itwillnotpersistwhen

either PRE or CLR returns to the inactive (high) level.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5

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