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54ACT11138FK PDF预览

54ACT11138FK

更新时间： 2024-02-09 17:19:42
品牌 Logo 应用领域
德州仪器 - TI 驱动输入元件输出元件逻辑集成电路
页数 文件大小 规格书
7页 91K
描述
IC ACT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CQCC20, CERAMIC, CC-20, Decoder/Driver

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54ACT11138FK 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFN包装说明：QCCN, LCC16,.3SQ
针数：20Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.91其他特性：3 ENABLE INPUTS; CENTER VCC/GND PINS
系列：ACTJESD-30 代码：S-CQCC-N20
长度：8.89 mm负载电容（CL）：50 pF
逻辑集成电路类型：OTHER DECODER/DRIVER最大I（ol）：0.024 A
功能数量：1端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：INVERTED封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装等效代码：LCC16,.3SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
Prop。Delay @ Nom-Sup：10.5 ns传播延迟（tpd）：10.3 ns
认证状态：Not Qualified座面最大高度：2.03 mm
子类别：Decoder/Drivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：8.89 mm
Base Number Matches：1

54ACT11138FK 数据手册

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54ACT11138, 74ACT11138  
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS  
SCAS050A – D3266, JANUARY 1989 – REVISED APRIL 1993  
54ACT11138 . . . J PACKAGE  
74ACT11138 . . . D, N, OR PW PACKAGE  
• Designed Specifically for High-Speed  
Memory Decoders and Data Transmission  
Systems  
(TOP VIEW)  
• Incorporates Three Enable Inputs to  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Y0  
A
B
Y1  
Y2  
Y3  
GND  
Y4  
Y5  
Simplify Cascading and/or Data Reception  
• Flow-Through Architecture Optimizes  
PCB Layout  
C
V
• Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
CC  
G1  
G2A  
G2B  
• EPIC (Enhanced-Performance Implanted  
Y6  
Y7  
CMOS) 1- m Process  
• 650-mA Typical Latch-Up Immunity  
at 125°C  
54ACT11138 . . . FK PACKAGE  
(TOP VIEW)  
• Package Options Include Plastic  
Small-Outline Packages, Plastic Thin  
Shrink Small-Outline Packages, Ceramic  
Chip Carriers, and Standard Plastic and  
Ceramic 300-mil DIPs  
3
2
1
20 19  
18  
4
5
6
7
8
G2A  
G2B  
NC  
Y7  
A
Y0  
NC  
Y1  
Y2  
17  
16  
15  
14  
description  
The ′ACT11138 circuit is designed to be used in  
high-performance memory-decoding or data-  
routing applications requiring very short  
propagation delay times. In high-performance  
memory systems, this decoder can be used to  
minimize the effects of system decoding. When  
employed with high-speed memories utilizing a  
fast enable circuit, the delay times of this decoder  
Y6  
9 10 11 12 13  
NC – No internal connection  
and the enable time of the memory are usually less than the typical access time of the memory. This means  
that the effective system delay introduced by the decoder is negligible.  
The conditions at the binary select inputs and the three enable inputs select one of eight input lines. Two  
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.  
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one  
inverter. An enable input can be used as a data input for demultiplexing applications.  
The 54ACT11138 is characterized for operation over the full military temperature range of – 55°C to 125°C. The  
74ACT11138 is characterized for operation from – 40°C to 85°C.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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