Datasheet > 54ACT109MDS

54ACT109MDS

更新时间： 2024-01-12 18:15:21

品牌	Logo	应用领域
德州仪器 - TI		输出元件逻辑集成电路触发器
页数	文件大小	规格书
12页	233K
描述
ACT SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC, DIE

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54ACT109MDS 技术参数

Connection Diagrams

Pin Assignment

for DIP and Flatpak

Pin Assignment

for LCC

DS100267-3

DS100267-4

Truth Table

(each half)

Inputs

Outputs

S_D

C_D

Toggle

Q₀

HIGH Voltage Level

LOW Voltage Level

N =

LOW-to-HIGH Transition

Immaterial

Q (Q ) Previous Q (Q ) before LOW-to-HIGH Transition of Clock

Logic Diagram (one half shown)

DS100267-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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123 4 5 6 7...12

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