54ACQ374MDA

更新时间： 2024-01-15 14:39:30

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54ACQ374MDA 数据手册

Connection Diagrams (Continued)

Pin Names

D₀–D₇

Description

Data Inputs

Clock Pulse Input

TRI-STATE Output Enable Input

TRI-STATE Outputs

O₀–O₇

Functional Description

Truth Table

The ’ACQ/’ACTQ374 consists of eight edge-triggered

flip-flops with individual D-type inputs and TRI-STATE true

outputs. The buffered clock and buffered Output Enable are

common to all flip-flops. The eight flip-flops will store the

state of their individual D inputs that meet the setup and hold

time requirements on the LOW-to-HIGH Clock (CP) transi-

tion. With the Output Enable (OE) LOW, the contents of the

eight flip-flops are available at the outputs. When the OE is

HIGH, the outputs go to the high impedance state. Operation

of the OE input does not affect the state of the flip-flops.

Inputs

Outputs

D_n

O_n

HIGH Voltage Level

LOW Voltage Level

Immaterial

High Impedance

N =

LOW-to-HIGH Transition

Logic Diagram

DS100239-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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