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54AC74LMQB PDF预览

54AC74LMQB

更新时间: 2024-02-13 14:25:30
品牌 Logo 应用领域
美国国家半导体 - NSC 输出元件逻辑集成电路触发器
页数 文件大小 规格书
10页 177K
描述
IC AC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20, CERAMIC, LCC-20, FF/Latch

54AC74LMQB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCN, LCC20,.35SQ
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.22
系列:ACJESD-30 代码:S-CQCC-N20
JESD-609代码:e0长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:70000000 Hz最大I(ol):0.012 A
位数:1功能数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
传播延迟(tpd):16 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:2.54 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:8.89 mm最小 fmax:95 MHz
Base Number Matches:1

54AC74LMQB 数据手册

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February 1993  
54AC/74AC74 54ACT/74ACT74  
#
Dual D-Type Positive Edge-Triggered Flip-Flop  
Asynchronous Inputs:  
LOW input to S (Set) sets Q to HIGH level  
General Description  
D
The ’AC/’ACT74 is a dual D-type flip-flop with Asynchro-  
nous Clear and Set inputs and complementary (Q, Q) out-  
puts. Information at the input is transferred to the outputs on  
the positive edge of the clock pulse. Clock triggering occurs  
at a voltage level of the clock pulse and is not directly relat-  
ed to the transition time of the positive-going pulse. After  
the Clock Pulse input threshold voltage has been passed,  
the Data input is locked out and information present will not  
be transferred to the outputs until the next rising edge of the  
Clock Pulse input.  
LOW input to C (Clear) sets Q to LOW level  
D
Clear and Set are independent of clock  
Simultaneous LOW on C and S makes both Q and Q  
D
D
HIGH  
Features  
Y
CC  
I
reduced by 50%  
Y
Y
Y
Output source/sink 24 mA  
’ACT74 has TTL-compatible inputs  
Standard Military Drawing (SMD)  
Ð ’AC74: 5962-88520  
Ð ’ACT74: 5962-87525  
Logic Symbols  
Connection Diagrams  
Pin Assignment  
for DIP, Flatpak and SOIC  
TL/F/9920–1  
TL/F/9920–2  
IEEE/IEC  
TL/F/9920–4  
Pin Assignment for LCC  
TL/F/9920–3  
Pin Names  
D , D  
Description  
Data Inputs  
1
2
CP , CP  
1
Clock Pulse Inputs  
Direct Clear Inputs  
Direct Set Inputs  
Outputs  
2
TL/F/9920–5  
C , C  
D1 D2  
S , S  
D1 D2  
Q , Q , Q , Q  
2
1
1
2
FACTTM is a trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9920  
RRD-B30M75/Printed in U. S. A.  

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