Datasheet > 530EB62M5000BGR

530EB62M5000BGR

更新时间： 2023-05-15 00:00:00

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
15页	265K
描述
LVPECL Output Clock Oscillator, 62.5MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

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530EB62M5000BGR 数据手册

Si530/531

Table 5. CLK± Output Period Jitter

Parameter

Period Jitter*

Symbol

Test Condition

RMS

Min

—

Typ

Max

—

Units

PER

for F < 160 MHz

OUT

Peak-to-Peak

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

Table 6. CLK± Output Phase Noise (Typical)

Configuration

81.25 MHz

LVDS

312.5 MHz

LVPECL

1066 MHz

LVPECL

Units

Output

Offset Frequency (f)

L (f)

–110

–127

–134

–136

–143

–147

n/a

–100

–115

–119

–123

–135

–144

–147

–87

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

–102

–107

–111

–121

–135

–142

dBc/Hz

10 MHz

100 MHz

Table 7. Absolute Maximum Ratings¹

Parameter

Supply Voltage

Symbol

Rating

–0.5 to +3.8

Units

Volts

ºC

Input Voltage (any input pin)

Storage Temperature

–0.5 to V + 0.3

–55 to +125

>2500

260

ESD Sensitivity (HBM, per JESD22-A114)

ESD

Volts

ºC

Soldering Temperature (Pb-free profile)

PEAK

Soldering Temperature Time @ T

(Pb-free profile)

seconds

PEAK

Notes:

1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions.

2. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including

soldering profiles.

Rev. 1.0

1 2 345 6 7...15

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