Datasheet > 530BB625M000DGR

530BB625M000DGR

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
12页	111K
描述
LVDS Output Clock Oscillator, 625MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

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530BB625M000DGR 数据手册

Si530/531

Table 4. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Min

—

Typ

0.25

0.26

0.36

0.34

0.62

0.61

Max

0.40

0.37

0.50

0.42

—

Units

Phase Jitter (RMS)¹

for F_OUT> 500 MHz

_J

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

12 kHz to 20 MHz (OC-48)

—

Phase Jitter (RMS)¹

for F_OUTof 125 to 500 MHz

—

50 kHz to 80 MHz (OC-192)

—

Phase Jitter (RMS)

for F_OUTof 10 to 160 MHz

CMOS Output Only

12 kHz to 20 MHz (OC-48)

—

50 kHz to 20 MHz

—

Notes:

1. Refer to AN256 for further information.

2. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,

2 MHz for 10 MHz < FOUT <50 MHz.

Table 5. CLK± Output Period Jitter

Parameter

Period Jitter*

Symbol

Test Condition

RMS

Min

—

Typ

Max

—

Units

PER

Peak-to-Peak

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

Table 6. CLK± Output Phase Noise (Typical)

Offset Frequency (f)

120.00 MHz

LVDS

156.25 MHz

LVPECL

622.08 MHz

LVPECL

Units

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

–112

–122

–132

–137

–144

–150

n/a

–105

–122

–128

–135

–144

–147

n/a

–97

–107

–116

–121

–134

–146

–148

dBc/Hz

10 MHz

100 MHz

Rev. 1.2

1 2 345 6 7...12

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