Datasheet > 530BA626M000DG

530BA626M000DG

更新时间： 2023-02-26 13:34:02

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
12页	111K
描述
LVDS Output Clock Oscillator, 626MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

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530BA626M000DG 数据手册

Si530/531

Table 2. CLK± Output Frequency Characteristics (Continued)

Parameter

Total Stability

Symbol

Test Condition

Min

—

Typ

—

Max

±20

Units

ppm

Temp stability = ±7 ppm

Temp stability = ±20 ppm

Temp stability = ±50 ppm

—

±31.5

±61.5

—

Powerup Time⁴

t_OSC

—

Notes:

1. See Section 3. "Ordering Information" on page 7 for further details.

2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

3. Selectable parameter specified by part number.

4. Time from powerup or tristate mode to f_O.

Table 3. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

mid-level

Min

V_DD– 1.42

1.1

Typ

—

Max

V_DD– 1.25

1.9

Units

LVPECL Output Option¹

V_OD

V_SE

swing (diff)

—

V_PP

swing (single-ended)

mid-level

0.55

—

0.95

LVDS Output Option²

CML Output Option²

1.125

1.20

1.275

swing (diff)

V_OD

V_O

0.5

—

0.7

0.9

—

V_PP

2.5/3.3 V option mid-level

1.8 V option mid-level

– 1.30

—

– 0.36

—

2.5/3.3 V option swing (diff)

1.8 V option swing (diff)

1.10

0.35

0.8 x V_DD

—

1.50

1.90

0.50

V_DD

0.4

350

—

V_PP

V_OD

0.425

—

CMOS Output Option³

Rise/Fall time (20/80%)

Symmetry (duty cycle)

V_OH

V_OL

= 32 mA

I_OL= 32 mA

—

t_R,t_F

LVPECL/LVDS/CML

—

CMOS with C = 15 pF

—

LVPECL:

V_DD– 1.3 V

SYM

(diff)

LVDS:

CMOS:

—

1.25 V (diff)

V_DD/2

Notes:

1. 50  to V_DD– 2.0 V.

2. R_term= 100  (differential).

3. C_L= 15 pF

Rev. 1.2

1 234 5 6 7...12

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