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5-330808-3 PDF预览

5-330808-3

更新时间: 2024-02-21 00:25:29
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
24页 776K
描述
14-Bit, 80 MSPS/105 MSPS A/D Converter

5-330808-3 技术参数

是否Rohs认证: 不符合生命周期:Active
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8536.69.40.40风险等级:5.71
联系完成配合:NOT SPECIFIED触点材料:NOT SPECIFIED
设备插槽类型:IC SOCKETBase Number Matches:1

5-330808-3 数据手册

 浏览型号5-330808-3的Datasheet PDF文件第16页浏览型号5-330808-3的Datasheet PDF文件第17页浏览型号5-330808-3的Datasheet PDF文件第18页浏览型号5-330808-3的Datasheet PDF文件第20页浏览型号5-330808-3的Datasheet PDF文件第21页浏览型号5-330808-3的Datasheet PDF文件第22页 
AD6645  
LAYOUT INFORMATION  
The schematic of the evaluation board (see Figure 43)  
represents a typical implementation of the AD6645. A multi-  
layer board is recommended to achieve best results. It is highly  
recommended that high quality, ceramic chip capacitors be  
used to decouple each supply pin to ground directly at the  
device. The pinout of the AD6645 facilitates ease of use in the  
implementation of high frequency, high resolution design practices.  
All of the digital outputs are segregated to two sides of the chip,  
with the inputs on the opposite side for isolation purposes.  
JITTER CONSIDERATIONS  
The SNR for an ADC can be predicted. When normalized to  
ADC codes, the following equation accurately predicts the SNR  
based on three terms: jitter, average DNL error, and thermal  
noise. Each of these terms contributes to the noise within the  
converter.  
SNR =1.76 −  
1/2  
2
2
2× 2 ×VNOISE rms  
1+ ε  
2
20log  
(
2π× fANALOG ×tj rms  
)
+
+
2n  
2n  
Care should be taken when routing the digital output traces. To  
prevent coupling through the digital outputs into the analog  
portion of the AD6645, minimal capacitive loading should be  
placed on these outputs. It is recommended that a fanout of  
only one gate should be used for all AD6645 digital outputs.  
where:  
f
ANALOG is the analog input frequency.  
t
j rms is the rms jitter of the encode (rms sum of encode source  
The layout of the encode circuit is equally critical. Any noise  
received on this circuitry results in corruption in the digitization  
process and lower overall performance. The encode clock must be  
isolated from the digital outputs and the analog inputs.  
and internal encode circuitry).  
ε is the average DNL of the ADC (typically 0.41 LSB).  
n is the number of bits in the ADC.  
V
NOISE rms is the voltage rms thermal noise that refers to the  
Table 8. Twos Complement Output Coding  
analog input of the ADC (typically 0.9 LSB rms).  
AIN Level  
VREF + 0.ꢀꢀ V VREF − 0.ꢀꢀ V Positive FS  
VREF VREF Midscale  
VREF − 0.ꢀꢀ V VREF + 0.ꢀꢀ V Negative FS  
AIN  
Output State Output Code  
Level  
For a 14-bit ADC, such as the AD6645, aperture jitter can  
greatly affect the SNR performance as the analog frequency is  
increased. Figure 42 shows a family of curves that demonstrate the  
expected SNR performance of the AD6645 as jitter increases.  
The chart is derived from the preceding equation.  
01 1111 1111 1111  
00 … 0/11 … 1  
10 0000 0000 0000  
For a complete discussion of aperture jitter, see the AN-756  
application note, Sampled Systems and the Effects of Clock Phase  
Noise and Jitter. The AN-756 application note can be found on  
www.analog.com.  
80  
AIN = 30MHz  
75  
AIN = 70MHz  
70  
AIN = 110MHz  
65  
AIN = 150MHz  
AIN = 190MHz  
60  
55  
0
0.1  
0.2  
0.3  
0.4  
0.5  
0.6  
JITTER (ps)  
Figure 42. SNR vs. Jitter  
Rev. D | Page 19 of 24  
 
 
 

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