PE4220
Product Specification
Figure 3. Pin Configuration (Top View)
Table 4. Absolute Maximum Ratings
Symbol
Parameter/Conditions
Min Max Units
1
2
3
4
8
7
6
5
VDD
RF1
GND
GND
RF2
VDD
Power supply voltage
-0.3
4.0
V
VDD
+ 0.3
CTRL
VI
TST
TOP
PIN
Voltage on any input
-0.3
-65
-40
V
°C
4220
Storage temperature range
150
85
GND
RFC
Operating temperature
range
°C
Input power (50ꢀ)
ESD voltage (Human Body
Model)
25
dBm
V
VESD
250
Table 2. Pin Descriptions
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Pin
No.
Pin
Name
Description
1
VDD
Nominal 3 V supply connection. A
bypass capacitor (100 pF) to the ground
plane should be placed as close as
possible to the pin
2
3
CTRL
GND
CMOS or TTL logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
Electrostatic Discharge (ESD) Precautions
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
4
5
6
RFC
RF2
Common RF port for switch (Note 1)
RF2 port (Note 1)
GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Latch-Up Avoidance
7
GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
8
RF1
RF1 port (Note 1)
Table 5. Control Logic Truth Table
Note 1: All RF pins must be DC blocked with an external
series capacitor or held at 0 VDC
Control Voltage
Signal Path
RFC to RF1
RFC to RF2
.
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
Table 3. DC Electrical Specifications
Parameter
Min
Typ
Max
Units
Control Logic
VDD Power Supply Voltage
2.7
3.0
3.3
V
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of VDD. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the VDD pin when the
control logic input voltage level exceeds VDD.)
IDD Power Supply Current
(VDD = 3V, VCNTL = 3)
30
40
µA
Control Voltage High
Control Voltage Low
0.7x VDD
V
V
0.3x VDD
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0028-09 │ UltraCMOS™ RFIC Solutions
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