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4001023042551W9T

更新时间： 2024-01-23 17:13:37
品牌 Logo 应用领域
威世 - VISHAY 电阻器
页数 文件大小 规格书
6页 94K
描述
Res,SMT,Thin Film,2.55K Ohms,150WV,.05% +/-Tol,-5,5ppm TC,2010 Case

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4001023042551W9T 技术参数

生命周期：ActiveReach Compliance Code：unknown
风险等级：5.48构造：Chip
端子数量：2最高工作温度：155 °C
最低工作温度：-65 °C封装高度：0.5 mm
封装长度：5.065 mm封装形式：SMT
封装宽度：2.54 mm包装方法：TR
额定功率耗散 (P)：0.5 W电阻：2550 Ω
电阻器类型：FIXED RESISTOR系列：PHR
尺寸代码：2010子类别：Fixed Resistors
技术：THIN FILM温度系数：-5,5 ppm/ °C
容差：0.05%工作电压：150 V
Base Number Matches：1

4001023042551W9T 数据手册

 浏览型号4001023042551W9T的Datasheet PDF文件第1页浏览型号4001023042551W9T的Datasheet PDF文件第3页浏览型号4001023042551W9T的Datasheet PDF文件第4页浏览型号4001023042551W9T的Datasheet PDF文件第5页浏览型号4001023042551W9T的Datasheet PDF文件第6页 
Space Applications Only  
PHR  
Vishay Sfernice  
www.vishay.com  
DIMENSIONS in millimeters  
A
D
D
B
C
E
E
DIMENSIONS  
B
VARIANT  
NUMBER  
STYLE  
A
C
D/E  
MIN.  
1.368  
1.758  
2.908  
4.898  
0.848  
MAX.  
1.672  
2.062  
3.212  
5.232  
1.152  
MIN.  
0.723  
1.143  
1.473  
2.413  
0.473  
MAX.  
0.977  
1.397  
1.727  
2.667  
0.727  
MIN.  
0.373  
0.373  
0.373  
0.373  
0.373  
MAX.  
0.627  
0.627  
0.627  
0.627  
0.627  
MIN.  
0.25  
0.25  
0.27  
0.35  
0.15  
MAX.  
0.51  
0.51  
0.53  
0.61  
0.35  
01, 05  
02, 06  
03, 07  
04, 08  
13, 14  
0603  
0805  
1206  
2010  
0402  
NOTION OF SINGLE LOT  
The homogeneity of lots is given by the front end lot numbers (primary process lot) and not by the date code.  
The date code is applied after completion of end of production testing. Parts coming from different lots might have same date  
code. A customer who needs lot homogeneity should mention on his order: SINGLE PRODUCTION LOT  
END OF PRODUCTION TESTING  
Mandatory testing performed at the end of the production process:  
• 100 % overload: Voltage 6.25 Pn x Rnor 2 UL whichever is less - duration 2 s  
• 100 % burn in: 168 h at Pn at 70 °C  
OPTIONS  
LOT VALIDATION TESTING  
For procurement of qualified components, lot validation testing is not required and shall only be performed if specifically  
stipulated in the purchase order.  
For procurement of unqualified components, lot validation testing shall be performed as stipulated in the purchase order. The  
need for lot validation testing shall be determined by the orderer.  
When lot validation testing is required, it shall consist of the performance of one or more of the tests or subgroup test sequences  
of chart F4 indicated in the ESA Generic Specification ESCC 4001. The testing to be performed and the sample size shall be as  
stipulated in the purchase order. When procurement of more than one component type is involved from a family, range or series,  
the selection of representative samples shall also be stipulated in the purchase order.  
Lot validation testing will be composed of one LVT charges and LVT samples:  
• Lot validation test charges has to be ordered separately on purchase order.  
• Lot validation samples have to be ordered separately on purchase orderer.  
FINAL INSPECTION  
If requested by the orderer a final inspection can be performed on site.  
Final inspection has to be stipulated separately on purchase order.  
LAND PATTERN in millimeters  
Gmin.  
X
Zmax.  
CHIP SIZE  
0402  
Zmax.  
1.55  
2.37  
2.76  
3.91  
5.93  
Gmin.  
0.15  
0.35  
0.74  
1.85  
3.71  
Xmax.  
0.73  
0.98  
1.40  
1.73  
2.67  
0603  
0705/0805  
1206  
2010  
Note  
Suggested land pattern: According to IPC-7351A  
•
Revision: 26-Mar-14  
Document Number: 53037  
2
For technical questions, contact: sferthinfilm@vishay.com  
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
123456

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